Paralleling devices is an effective way to achieve higher power application while still having the convenience of using discrete devices. However, the mechanisms of potential failures and the circuit design considerations has not been thoroughly studied yet, when paralleling Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) in cascode configuration. This paper presents a comprehensive study on paralleled high voltage cascode GaN HEMTs, evaluating both circuit design and device characteristic. The mechanisms of current oscillation, which occurred during the cascode GaN HEMTs parallel operation, are analyzed in detail. The Q3D tool and SPICE-based simulation model jointly quantify the sensitivity of the circuit parasitic parameters and the cascode GaN HEMTs mismatches during the paralleled operation. General design guidelines are provided in the paper as well. A group of experimental results ultimately validate the analysis toward parallel operation.

Paralleling devices is an effective way to achieve higher power applications while still having the convenience brought by discrete devices. However, very few papers investigate the challenges of paralleling Gallium Nitride high electron mobility transistors (GaN HEMTs) in cascode configuration, especially the potential failure modes and its related mechanisms. In this paper, a comprehensive study on paralleled high voltage cascode GaN HEMTs is presented. The influence of paralleling cascode GaN HEMTs on the circuit's stray inductance is studied. Potential operation failure modes and the mechanisms of the cascode GaN HEMTs parallel operation were analyzed in detail. The Ansoft Q3D FEA tool and SPICE-based simulation model were used together to quantify the impacts of the circuit and device mismatch on the paralleled GaN HEMTs operation. The SPICE model is validated by the experimental results