Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times

Stratigopoulos, Haralampos-G.; Barragán, Manuel J.; Mir, Salvador; Gall, Herve Le; Bhargava, Neha; Bal, Ankur

doi:10.1109/test.2015.7342385

Cited by 7 publications

(5 citation statements)

References 28 publications

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“…In this case, none of the above methods is practical since they require simulating at least hundreds of circuit samples at the transistor level. For circuits with long simulation times, yield estimation is typically carried out by first developing a behavioral model that captures effectively the circuit functionality and then applying any of the above methods by considering the behavioral-level description of the circuit instead of the transistor-level or layout-level description [26], [27]. A behavioral model is constructed by decomposing the circuit into independent sub-circuits, creating a separate behavioral model for each sub-circuit to reflect its functionality, and then linking these behavioral models and manipulating the data flow so as to compute the circuit performances.…”

Section: E Behavioral Modelingmentioning

confidence: 99%

“…Another approach is to use the data in (27) as a training set and learn a regression model to express wafer yield as a function of the e-tests for device N…”

Section: B Early Learningmentioning

confidence: 99%

“…C. Naive mixing of data A third approach is to naively mix data in (26) and (27), use the combined data as a training set, and learn a regression model to express wafer yield as a function of the e-tests…”

Section: B Early Learningmentioning

confidence: 99%

See 2 more Smart Citations

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

Ahmadi

Stratigopoulos

Huang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up and fast time-to-market. To date, yield estimation is generally performed through simulationbased methods. However, such methods are not only very timeconsuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits. In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them towards predicting yield during (i) production migration from one fabrication facility to another, and (ii) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of process design kit accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65nm RF transceiver devices.

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Section: E Behavioral Modelingmentioning

confidence: 99%

“…Another approach is to use the data in (27) as a training set and learn a regression model to express wafer yield as a function of the e-tests for device N…”

Section: B Early Learningmentioning

confidence: 99%

See 1 more Smart Citation

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

Ahmadi

Stratigopoulos

Huang

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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“…The theoretical principles behind the concepts of ternary test stimulus generation and injection were described in [17] and were validated using behavioral model simulations. The feasibility and suitability of the ternary test stimulus for highvolume production test was further validated in [18], [19] by means of parametric test metrics estimation techniques based also on behavioral model simulations.…”

Section: Previous Workmentioning

confidence: 99%

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Barragán

Alhakim

Stratigopoulos

et al. 2016

IEEE Trans. Circuits Syst. I

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This paper proposes a fully-digital BIST architecture for the dynamic test of Σ∆ ADCs. The proposed BIST relies on generating a ternary stream that encodes a high-linearity analog sinusoidal and injecting it directly at the input of the Σ∆ modulator. Compared to the well-known bitstream, the use of three logic levels in the ternary stream reduces the quantization noise and, thereby, results in a test with a higher dynamic range that covers the full scale of the ADC. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNDR. A standard SPI bus provides digital external access to the embedded test instruments. The proposed BIST wrapper has been integrated into a 40 nm CMOS 18-bit stereo audio Σ∆ ADC IP core provided by ST Microelectronics. It incurs an overall area overhead of 7.1% and the total test time is 28ms per channel. Experimental results on fabricated chips demonstrate an excellent correlation between the BIST and the standard functional specification test.

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“…The distinction in the process of test generation appears as being important in the context of the recent developments in the field of analog testing. With the arrival of software enabling the automated computation of fault coverages [11], [13], it becomes possible to integrate a quality assessment step in the design flow of analog integrated circuits. The test designer knows to what extent an IC is actually tested and the list of faults which are not yet detected by the test program at hand is made available.…”

Section: Fault-centered Approachmentioning

confidence: 99%

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis

Coyette

Esen

Dobbelaere

et al. 2016

2016 IEEE International Test Conference (ITC)

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A method is presented to address the automatic generation of test signals for analog and mixed-signal integrated circuits. No restriction on the number of inputs or the nonlinearity of the circuit are made. The circuit under consideration is first decomposed into a set of sub-circuits, called blocks, in order to break down the complexity of the problem. The effect of a targeted fault is then automatically analyzed at the transistor level in a defect-oriented context. From this analysis, the fault sensitization conditions are extracted and then backtraced towards the primary inputs or outputs of the circuit using an algorithm based on the interval analysis theory. The underlying algorithms supporting the automation of the whole procedure are illustrated for basic circuits. Finally, in order to demonstrate the method, an industrial circuit is used as case study. It is shown that test signals can be generated in order to achieve a fault coverage of 98%.

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Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times

Abstract: International audienc

Cited by 7 publications

References 28 publications

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis

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