Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

Wang, H.-B.; Kauppila, J. S.; Lilja, K.; Bounasser, M.; Chen, Li; Newton, Michael; Li, Y.-Q.; Liu, R.; Bhuva, B. L.; Wen, Shi-Jie; Wong, Richard; Fung, Rita; Baeg, Sanghyeon; Massengill, L.W.

doi:10.1109/tns.2016.2630022

Cited by 32 publications

(11 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They also report a difference of two orders of magnitude in sensitivity to heavy ions when comparing their FD-SOI test chip to a CMOS bulk counterpart. [14] reports similar results from experiments carried out on D flip-flops from a 28 nm UTBB FD-SOI test chip.…”

Section: A Radiation Focused Experimental State-of-the-artsupporting

confidence: 57%

See 1 more Smart Citation

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

At first used to emulate the effects of radioactive ionizing particules passing through integrated circuits (ICs), laser illumination is also used to inject faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser faults injection than the more usual CMOS bulk technology. We report in this work an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges.

show abstract

Section: A Radiation Focused Experimental State-of-the-artsupporting

confidence: 57%

“…There are many papers highlighting, often on experimental basis, the advantages of SOI or FD-SOI over CMOS bulk regarding sensitivity to SEEs [8]- [14]. These experimental results were mostly obtained on elementary test elements (either transistors or logic gates), and partly conducted with laser emulation.…”

Section: Introductionmentioning

confidence: 99%

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Dutertre

Beroulle

Candelier

et al. 2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

View full text Add to dashboard Cite

show abstract

“…The basic sampling, keeper circuit, and C-element parts are used to implement the hybrid FF. From related works [25][26][27][28][29][30][31][32][33][34][35], authors have focused to discuss the SEE effects only, another solution is C-element, which is proposed in [35] to overcome the SEE effects such as SET, and SEU in hybrid FF design. The hybrid pulsed FF, using C-element as a fundamental stage, provides better result to resist switching activity and improves data activity.…”

Section: Problem Definitionmentioning

confidence: 99%

“…From related works, the sequential CMOS circuits are affected by SEU [26–28, 31, 34] and SET [28–30, 33]. The sources of these effects are introduced from radiation errors.…”

Section: Problem Definition and System Modelmentioning

confidence: 99%

See 1 more Smart Citation

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Kamalakannan¹,

Venkatachalam²

2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip-flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

show abstract

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Islam

2018

J Electron Test

View full text Add to dashboard Cite

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and larger die sizes. The technology scaling followed Moore's law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flipflops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C 2 -DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Postlayout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1-5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

show abstract

Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

Cited by 32 publications

References 16 publications

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Contact Info

Product

Resources

About