Evaluation of SRAM faulty behavior under bit line coupling

Abstract

The faulty behavior of memory devices has traditionally been evaluated in isolation of the parasitic effects present on chip. As these effects become more dominant, however, they start to negatively influence the fault coverage of commonly used memory tests. This paper studies the way bit line coupling affects the faulty behavior of SRAM devices. Spice simulations are used to show how coupling can prevent the detection of otherwise detectable faults. Furthermore, an evaluation is done of the needed bit line coupling conditions to guarantee a high fault coverage of a given defect. This is done by identifying the most stressful data background patterns in the neighborhood of the faulty cell.

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling

“…An analytical evaluation of the CC BL effect is presented in [3][4] [5]. The analysis is based on a 3x3 memory cell array which was designed using the transistor models of the 65nm BSIM4 spice model.…”

“…Figure 1. SRAM electrical Spice model [4] [5] Considering the read operation, it has been shown in [3][4] [5] that the coupling capacitance Cb causes neighboring BLs to have an influence on the voltage development only when reading from a cell. This effect can impact the proper sense amplifier operation, which results in an incorrect read data (while the stored value is still correct).…”

“…In [3][4] [5], it has been shown that when accessing an SRAM cell containing a logic '1', the most stressful background is '11' in the neighboring cells connected to the same WL. It means that both left and right neighboring cells have to be set to logic '1' to maximize the effect of CC BL when reading the content of the middle cell.…”

Bit line coupling memory tests for single-cell fails in SRAMs

“…However, this test does not detect all targeted FFMs. Another well-known test that satisfies the BL coupling detection requirement is Scan = [3]. Again, Scan can only detect a limited number of single-cell static faults.…”