Evaluation on power reduction applying gated clock approaches

Palumbo, G.; Pappalardo, F.; Sannella, S.

doi:10.1109/iscas.2002.1010394

Cited by 35 publications

(13 citation statements)

References 9 publications

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“…An increased variability of multi-V th in nano-meter CMOS technology also makes design difficult. On top of these drawbacks, the conventional single-and dual-supply clock networks described above do not adopt any clock gating [2,3], an efficient power saving method. Unfortunately, incorporating a clock gating capability into these conventional clock networks causes a large design overhead, as seen in Section 3.…”

Section: Previous Workmentioning

confidence: 99%

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Low-power dual-supply clock networks with clock gating and frequency doubling

Lee

Kim

Han

et al. 2012

IEICE Electron. Express

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Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32 nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%. Keywords: dual supply, clock gating, level converting, clock distribution Classification: Integrated circuits References[1] J. Pangjun, et al., "Low-power clock distribution using multiple voltages and reduced swings,"

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Section: Previous Workmentioning

confidence: 99%

“…If the clock frequency could be scaled down, more power saving could be achieved. Proper clock gating could also be used to minimize the power consumption by reducing the switching activity of clock nets [2,3].…”

Section: Introductionmentioning

confidence: 99%

Low-power dual-supply clock networks with clock gating and frequency doubling

Lee

Kim

Han

et al. 2012

IEICE Electron. Express

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“…Well known methods for the purpose include voltage scaling [10], [11], switching activity reduction [12], [13], and logic optimization [14], [15]. However, these methods are not suitable in many applications such as portable computing gadgets, medical electronics etc., where ultra-low power consumption at medium frequency of operation is the primary requirement.…”

Section: Introductionmentioning

confidence: 99%

Interconnect Repeater Design for Portable Applications

Sharma¹,

Sharma²,

Arora³

et al. 2010

AIP Conference Proceedings

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-The length of interconnect and number of repeaters increases with increasing complexity of the VLSI chip. The power delay product and frequency of operation plays significant role in designing of repeater. Earlier proposed low-voltage swapped-body (LVSB) bias buffer [4] design shows better performance than the earlier conventional No-Body-Bias (NBB) buffer. Sub-threshold grounded-body (STGB) bias buffer design [1] proves even better than the LVSB buffer design in sub-threshold region for medium frequency applications as per the simulation results at 180 nm -90nm technologies.

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“…G. Palumbo has shown that manual CG can save more power than automated CG [7]; however it is not clear in the paper which automated CG strategy has been utilized. The advantage of using automated synthesis over manual CG is obvious because automated CG can be easily applied with fewer or no modification in HDL coding and can directly be applied at gate-level.…”

Section: Introductionmentioning

confidence: 99%

Complex clock gating with integrated clock gating logic cell

Bhutada

Manoli

2007

2007 International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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Clock gating is an effective technique for minimizing dynamic power in sequential circuits. Applying clock-gating at gate-level not only saves time compared to implementing clock-gating in the RTL code but also saves power and can easily be automated in the synthesis process. This paper presents simulation results on various types of clock-gating at different hierarchical levels on a Serial Peripheral Interface (SPI) design. In general power savings of about 30% and 36% reduction on toggle rate can be seen with different complex clockgating methods with respect to no clock-gating in the design.

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Evaluation on power reduction applying gated clock approaches

Cited by 35 publications

References 9 publications

Low-power dual-supply clock networks with clock gating and frequency doubling

Low-power dual-supply clock networks with clock gating and frequency doubling

Interconnect Repeater Design for Portable Applications

Complex clock gating with integrated clock gating logic cell

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