Event-Driven Modeling and Simulation of an Digital PLL

Zhuang, Jingcheng; Du, Qingjin; Kwaśniewski, T.

doi:10.1109/bmas.2006.283472

Cited by 18 publications

(11 citation statements)

References 6 publications

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“…Such enlarged phase error samples produced by the DTC are then quantized by the narrow-range TDC and filtered by the digital loop filter before modulating the DCO frequency and phase. To confirm the analysis, the phase noise performance of the PP-ADPLL is simulated in time-domain using an event-driven method [8] that introduces realistic phase noise sources into the DCO and reference clocks. Different K DT C errors are introduced in the phase prediction block and the time-domain edge jitter for different K DT C errors is converted to frequency-domain phase noise through spectral estimation routines with a 30 kHz resolution bandwidth.…”

Section: A Impact Of K Dt C Error On Pp-adpll Phase Noisementioning

confidence: 99%

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

Zhuang

Staszewski

2013

2013 European Conference on Circuit Theory and Design (ECCTD)

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We propose a gain estimation technique of a digitalto-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.

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Section: A Impact Of K Dt C Error On Pp-adpll Phase Noisementioning

confidence: 99%

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

Zhuang

Staszewski

2013

2013 European Conference on Circuit Theory and Design (ECCTD)

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“…The event-driven nature of the simulation results in drastically shorter simulation times compared to time-driven simulation using for instance Spice (Zhuang et al, 2006). This modeling technique does not suffer from the convergence issues usually observed with other techniques because it uses digital simulation environments (ModelSim, NCSim,…).…”

Section: Top-simulation and Modelingmentioning

confidence: 99%

Smart Bolometer: Toward Monolithic Bolometer with Smart Functions

Denoual

Allègre

Attia³

et al. 2012

Bolometers

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“…The ADPLL architecture described above is modeled and simulated in Matlab using time-domain event-driven principles [42], [43]. For simplicity, the PLL is configured as a type-II secondorder loop with proportional and integration paths (without the IIR filter of Fig.…”

Section: Behavioral Simulationmentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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Event-Driven Modeling and Simulation of an Digital PLL

Cited by 18 publications

References 6 publications

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

Smart Bolometer: Toward Monolithic Bolometer with Smart Functions

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

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