Ever-increasing role of mask technology in deep submicron lithography

Abstract

The role of mask technology is going through a major change as silicon technology moves into the sub O.5i,m regime and optical lithography continues to be the predominant approach. Several possible options are being considered such as DUV, PSM, oblique illumination, optical proximity correction (OPC), or some combination of these methods. In addition to tighter mask requirements, a significant challenge by itself, there are unique mask technology development issues to support each lithography option. Practically speaking, masks for the sub O.5Oim lithography regime are becoming less commodity products and more an integral part of the front end silicon technology development. Mask technology is foreseen to have an increasingly important role in the O.35im and O.25im technology generations and beyond.In this paper, we will first describe the role of mask technology in the sub O.5.tm lithography regime by examining the technology roadmap, specification requirements, and the mask impact on lithographic performance. Secondly, we will describe the major technical challenges facing mask technology and fabrication. Examples will be given. Lastly, we will suggest how to meet these challenges to satisfy the needs of silicon technology.

Patterning 80-nm gates using 248-nm lithography: an approach for 0.13-μm VLSI manufacturing

“…The become more important when operating near diffraction limits or in a low k1 process. Nonlinear imaging or mask error enhancement factor (MEEF) arises from stepper optics and the resist process has been studied extensively since the 90's 8,9,10 , and has attracted more attention from both mask and wafer lithography process engineers in recent years. Figure 13 shows the MEEF plot for the dense sub-100nm patterning process with a binary mask and a strong PSM.…”