Every walk’s a hit: making page walks single-access cache hits

Abstract

As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB page table nodes into a single 2 MB node, thereby reducing the table's depth and the number of indirections required to traverse it. The second is accomplished by biasing the cache replacement algorithm to keep page table entries during periods of high TLB miss rates, as these periods also see high data miss rates and are therefore more likely to benefit from having the smaller page table in the cache than to suffer from increased data cache misses.We evaluate these approaches for both native and virtualized systems and across a range of realistic memory fragmentation scenarios, describe the limited changes needed in our kernel implementation and hardware design, identify and address challenges related to self-referencing page tables and kernel memory allocation, and compare results across server and mobile systems using both academic and industrial simulators for robustness.We find that flattening does reduce the number of accesses required on a page walk (to 1.0), but its performance impact (+2.3%) is small due to Page Walker Caches (already 1.5 accesses). Prioritizing caching has a larger effect (+6.8%), and the combination improves performance by +9.2%. Flattening is more effective on virtualized systems (4.4 to 2.8 accesses, +7.1% performance), due to 2D page walks. By combining the two techniques we demonstrate a state-ofthe-art +14.0% performance gain and -8.7% dynamic cache energy and -4.7% dynamic DRAM energy for virtualized execution with very simple hardware and software changes. CCS CONCEPTS• Computer systems organization → Architectures; • Software and its engineering → Virtual memory.

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

“…Unfortunately, as pointed out in the prior study [18], the efficiency of the PSC varies according to the locality of the memory references, and it rarely performs effectively for workloads with irregular access patterns. When a PSC VOLUME 4, 2016 iii This article has been accepted for publication in IEEE Access.…”

“…In the best case, if VA[56:21] is matched on the PD-PSC (PSC holding the entries of the PD table), the 5-step page walk is reduced to just a single step. On average, the PSC enables to skip 2.2 ∼ 2.9 steps in the 4-level page walk [18].…”

“…Memory accesses triggered by page walks can account for up to 20∼40% of total memory accesses [20]. Recent studies have pointed out that address translations requiring many memory accesses are the primary performance bottleneck [18], [29], [30], [33], [34], [42], [43].…”

“…There has been a large body of prior works on mitigating the overheads of page walk by reducing TLB misses [15], [21]- [30] or by reducing TLB miss penalty [13], [16], [18], [31]- [35]. This paper focuses on the second approach.…”

“…Even if CSALT is an efficient method that provides dedicated on-chip storage for holding the address translation information, it relies on their specific memory system architecture (i.e., POM-TLB). More recently, Park et al [18] proposed a method called page table prioritization (PTP) to prioritize cache blocks so that cache blocks containing PSEs (PSE blocks) reside in the on-chip cache. The basic idea of PTP is similar to ours.…”