Evolution of Low Drop Out Voltage Regulator in CMOS Technologies

Mustafa, Norhaida Binti; Amin, Syedul; Reaz, Mamun Bin Ibne; Hashim, Fazida Hanim; Kamal, Noorfazila

doi:10.15199/48.2015.12.06

Cited by 4 publications

(3 citation statements)

References 26 publications

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“…In PMOS based regulator, PMOS transistor is configured as common source amplifier. The voltage difference between input and output terminals is the minimum voltage required to keep MOSFET in saturation region, which is typically around 50 mV to 200 mV [5]- [8]. Hence, PMOS based voltage regulators are called Low Drop Out (LDO) voltage regulators and their power efficiency is comparable with switching regulators [9]- [11].…”

Section: Fig 1 Basic Block Diagram Of Linear Voltage Regulatormentioning

confidence: 99%

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Guruprasad

2024

jes

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In his article, a comparative analysis of PMOS and NMOS based linear voltage regulators is presented. An output power of 18 mW is considered in the both cases. In PMOS based regulator, the output voltage is 1.6 V and output current is 11.25 mA, whereas in NMOS, they are 1 V and 18 mA respectively. Firstly, a conventional linear regulator is designed with PMOS as pass element and its stability and various performance parameters are analyzed. SPICE simulation is carried out to measure parameters and they are tabulated for the comparison. Similarly, another linear regulator is designed where pass element is a NMOS transistor. After the analysis of stability and performance parameters, SPICE simulation is conducted. The performance parameters of both regulators are compared and it is found that NMOS regulator exhibits better performance but low dropout feature of PMOS regulator makes it suitable for low power applications.

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Section: Fig 1 Basic Block Diagram Of Linear Voltage Regulatormentioning

confidence: 99%

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Guruprasad

2024

jes

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“…To avoidd such problem CMOS Low-drop-out voltage regulator are used. LDO design has gotten more difficult as the demand for highly effective performance LDO's has grown, with low voltage and quick settled transient LDO, being particularly significant [1] as it is classified as small dropout, small supply current, huge supply current, high speed and excessive voltage [3]. The speed and power consumption are the two main factors for today portable applications [4].…”

Section: Introductionmentioning

confidence: 99%

Design of Low-Drop-Out Voltage Regulator using CMOS Technology for Microprocessor Applications

Kusumanchi,

Ernest Ravindran,

Jaya Sankar Krishna

et al. 2023

J. Phys.: Conf. Ser.

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The demand for electronic devices has increased due to continuous change in technology and its parameters. Low-Drop-Out [LDO] voltage regulator is utilised for power management and avoids unstable voltage in many electronicapplications.In this present investigation, a comprehensive characterization of a LDO in Complementary metal oxide semi-conductor technology [CMOS] is simulated using mentor graphics tool. The error amplifier of the low-drop-out voltage employed using 7 transistors for current mirroring technique. To manage the voltage differential, a pass transistor is created in a similar way utilising PMOS. Resistors and capacitors are passive components used in feedback network circuits and to reduce output voltage volatility, respectively. The suggested circuit achieves 140 mV of dropout voltage with a constant voltage of 1.6 V with a supply voltage range of 2 to 4.2 V and 4.16 mW of power consumption..

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“…A linear regulator can provide high-speed variations in the output signal and can generate a faster load transient response. Moreover, it causes poor performance in current efficiency when the low drop output is large [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

et al. 2022

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Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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Evolution of Low Drop Out Voltage Regulator in CMOS Technologies

Cited by 4 publications

References 26 publications

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Comparative Analysis of PMOS and NMOS based Linear Regulators with Similar Power Profiles

Design of Low-Drop-Out Voltage Regulator using CMOS Technology for Microprocessor Applications

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

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