Evolution of Stress During Formation of Titanium Disilicide by Rta and Tube Furnace Annealing

Abstract

Integrated circuit fabrication consists of many processing steps: e.g. lithography, etching, implantation and metallization. Some of these processes are combined with thermal processing. Heat treatments require special attention because previous fabrication steps may be influenced: e.g. dopant profiles may be deteriorated. The amount of interference of an annealing step with a former process is determined by the ratio of the reaction rates (and hence by the difference in activation energies).

Characterization of the local mechanical stress induced during the Ti and Co/Ti salicidation in sub-0.25 μm technologies

“…21 However, during as well the formation of the TiSi 2 film as during the formation of the CoSi 2 film, an intrinsic compressive stress is introduced in the film as shown in Fig. 5.…”

Modeling of local reduction in TiSi/sub 2/ and CoSi/sub 2/ growth near spacers in MOS technologies: influence of mechanical stress and main diffusing species

“…7) estimated at 5.10'O dyne/cm2 [5,6]. In order to overcome these deficiencies, two effects have been considered: the reduction in atom diffusivity under mechanical stress and the stress relaxation : Firstly, an Arrhenius law for the stress relaxation time has been deduced from experimental results [7], leading to an extrapolated value of about 0.25 sec at 730°C, and a drop in pressure below the elasticity limit as shown in Fig. 8.…”