Evolvability and reconfigurability

Santini, Cristina Costa; Amaral, J.F.M.; Pacheco, Marco Aurélio Cavalcanti; Tanscheit, Ricardo

doi:10.1109/fpt.2004.1393257

Cited by 6 publications

(4 citation statements)

References 22 publications

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“…20 and 21 resulting in expressions for the sensitivities depending only on the frequency x. S6. In order to find the frequency, x max , that maximizes the sensitivities, the derivatives of (20) and (21) v Fig. 16 a Direct-form realization of the first-order filter of the example b corresponding adjacency matrix representation and c equations system derived from the adjacency matrix respect to x are equated to zero.…”

Section: The Fitness Computation Examplementioning

confidence: 99%

“…These algorithms have recently attracted the researcher's attention due to their success in synthesizing large classes of analog [5][6][7][8][9][10][11][12][13] and digital [14][15][16][17][18] circuits. In contrast with traditional synthesis methods, evolutionary synthesis has the desirable property of including the circuit topology as a variable of overall synthesis problem, opening the opportunity of approaching some complex circuit design issues as selfadaptation, self-repairing and self-reconfiguration [19,20].…”

Section: Introductionmentioning

confidence: 99%

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Evolutionary synthesis of low-sensitivity digital filters using adjacency matrix

Sá

Mesquita

2009

Evol. Intel.

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An evolutionary synthesis method to generate digital filters with low coefficient sensitivity is presented. The method uses a chromosome coding based on the graph adjacency matrix representation. It is shown that the proposed chromosome representation enables to easily verify and avoid the generation of topologically invalid and noncomputable individuals during the evolutionary process. The efficiency of the proposed algorithm is tested in the synthesis of two low-pass digital filters and the results are compared with other examples found in the literature.

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Section: The Fitness Computation Examplementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evolutionary synthesis of low-sensitivity digital filters using adjacency matrix

Sá

Mesquita

2009

Evol. Intel.

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“…Function-level evolution has been further extended in [67]. Although the proposed approach significantly reduces the number of generations required to obtain a fully functional solution, the evolvability [46], [48], [49] of logic circuits with a higher number of inputs remains the central issue.…”

Section: Scalability Problems and Stalling Effect In The Fitness mentioning

confidence: 99%

“…• Increasing the evolvability [46]- [49]. Evolvability, as defined in [52] is the ability of the genetic operator/representation scheme to produce offsprings that are fitter than their parents.…”

mentioning

confidence: 99%

Generalized Disjunction Decomposition for Evolvable Hardware

Stomeo¹,

Kalganova²,

Lambert³

2006

IEEE Trans. Syst., Man, Cybern. B

101

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Abstract-Evolvable hardware (EHW) refers to selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + λ) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.Index Terms-Adaptive system, evolutionary computation, evolvable hardware (EHW), problem decomposition.

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Advanced High Performance Computing for Big Data Local Visual Meaning

Aksu

2017

Big Data and Visual Analytics

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Evolvability and reconfigurability

Cited by 6 publications

References 22 publications

Evolutionary synthesis of low-sensitivity digital filters using adjacency matrix

Evolutionary synthesis of low-sensitivity digital filters using adjacency matrix

Generalized Disjunction Decomposition for Evolvable Hardware

Advanced High Performance Computing for Big Data Local Visual Meaning

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