Evolvable multi-processor: a novel MPSoC architecture with evolvable task decomposition and scheduling

Vakili, Shervin; Fakhraie, S.M.; Mohammadi, Siamak

doi:10.1049/iet-cdt.2008.0120

Cited by 9 publications

(8 citation statements)

References 12 publications

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“…some DSP applications have developed and evaluated on EvoMP in [8]. In this paper, we have performed same study for artificial neural network (ANN), which is the most applicable algorithm in pattern recognition applications.…”

Section: Resultsmentioning

confidence: 99%

“…It means that this platform does not require parallel programming or compile-time parallelization, because these operations are performed at run-time by hardware. A comprehensive description of architectural and operational aspects of EvoMP is presented in [8] (where it is introduced for the first time) in which some DSP applications are studied for experimental results. This paper contains the same study and performance evaluation for neural networks, which are one of the most commonly used algorithms in pattern recognition and artificial intelligence applications.…”

Section: Introductionmentioning

confidence: 99%

“…A sample of scheduling data (chromosome) for 2-tap FIR filter program and corresponding execution scheme[8].…”

mentioning

confidence: 99%

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Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling: A neural network case study

Vakili

Fakhraie

Mohammadi

2008

2008 International Conference on Innovations in Information Technology

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Decomposition of programs into concurrent tasks and scheduling them among computational recourses are two major problems in hardware and software developments of multiprocessor systems. This paper presents a novel homogeneous multiprocessor architecture, in which a hardware core performs these two jobs at run-time using genetic algorithm. This core looks for an efficient decomposition and scheduling scheme for the running application based on available computational resources. The main novel feature of this system is its capability of executing uni-processor sequential programs directly by cooperation of all available processors. This system is called EvoMP (Evolvable MultiProcessor) and recently introduced in detail by the authors (in another literature). This paper presents a brief description of the operational and architectural aspects of EvoMP and studies applicability of this platform for neural network applications.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling: A neural network case study

Vakili

Fakhraie

Mohammadi

2008

2008 International Conference on Innovations in Information Technology

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“…If R Z and R Y are rotation matrices around the z-axis and y-axis with α j and β j sizes, respectively, these rotation matrices can rotate the vector v I to match the z-axis. R Z and R Y are obtained by Equation (2).…”

Section: Theoremmentioning

confidence: 99%

TLP: Towards three‐level loop parallelisation

Mahjoub

Golsorkhtabaramiri

Amiri

2022

IET Computers & Digital Tech

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Due to the design of computer systems in the multi‐core and/or multi‐processor form, it is possible to use the maximum capacity of processors to run an application with the least time consumed through parallelisation. This is the responsibility of parallel compilers, which perform parallelisation in several steps by distributing iterations between different processors and executing them simultaneously to achieve lower runtime. The present paper focuses on the uniformisation of three‐level perfect nested loops as an important step in parallelisation and proposes a method called Towards Three‐Level Loop Parallelisation (TLP) that uses a combination of a Frog Leaping Algorithm and Fuzzy to achieve optimal results because in recent years, many algorithms have worked on volumetric data, that is, three‐dimensional spaces. Results of the implementation of the TLP algorithm in comparison with existing methods lead to a wide variety of optimal results at desired times, with minimum cone size resulting from the vectors. Besides, the maximum number of input dependence vectors is decomposed by this algorithm. These results can accelerate the process of generating parallel codes and facilitate their development for High‐Performance Computing purposes.

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“…To solve the constraints imposed by the market, the recent progress in microelectronics technology has provided many solutions. Now, it is possible to develop complex embedded systems, which contain many microprocessors (central processing units [CPUs]), different types of memories, communication among system components and slave circuits on the same chip, such as multiprocessor system on chip (MPSoC) technology [1, 2]. The MPSoC architectures are usually devoted to applications which require intensive computation.…”

Section: Introductionmentioning

confidence: 99%

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Belhadj

Bahri

Marrakchi

et al. 2015

IET Computers & Digital Techniques

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Evolvable multi-processor: a novel MPSoC architecture with evolvable task decomposition and scheduling

Cited by 9 publications

References 12 publications

Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling: A neural network case study

Designing an MPSoC architecture with run-time and evolvable task decomposition and scheduling: A neural network case study

TLP: Towards three‐level loop parallelisation

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

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