“…As this approach is not beneficial in terms of cost and manufacturing complexity, several chip-level ESD mitigation strategies have been studied and adopted. These include, not being limited to, the tuning of the electron blocking layer thickness, [139] the insertion of a current blocking layer, [140,141] the modification of the epitaxial structure, [142,143] the improvement of the mesa isolation, [144] the reduction in concentration of V-shaped defects in the active region, [145] the optimization of the electrodes, [146] and the addition of floating guard rings. [147] If the temporal duration of the unwanted bias state exceeds the microsecond scale, the condition is referred to as conventional EOS event.…”