Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips

Nakahara, Hiroyuki; Ozaki, Tomoya; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu

doi:10.1109/mcsoc.2015.26

Cited by 1 publication

(2 citation statements)

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“…Parameters for the full system simulation are shown in Table 2. (3,3,6) on the T [4,4,8] to make the best use of the inter-chip network. L2 cache is allocated on the other nodes.…”

Section: Evaluation Of the Case Of Single Corementioning

confidence: 99%

“…To connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed that enable the system to be extended to x or/and y dimensions, not only to z dimension [2], [3]. They interestingly allow to incrementally add chips to existing stacked chip systems and allows to optimize stacking to a target application on demand.…”

Section: Introductionmentioning

confidence: 99%

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Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface

Nakahara

Ozaki

Matsutani

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARYThe increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh. key words: inductive coupling interconnect, interconnection network, network on chip

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“…Parameters for the full system simulation are shown in Table 2. (3,3,6) on the T [4,4,8] to make the best use of the inter-chip network. L2 cache is allocated on the other nodes.…”

Section: Evaluation Of the Case Of Single Corementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%