Expansion of the Junction Temperature Measurement via the Internal Gate Resistance to a wide range of Power Semiconductors

Junction Temperature Measurement Based on the Internal Gate Resistance for a Wide Range of Power Semiconductors

“…The principle of the measurement method has been first described in [48]. A driver-integrated solution has been demonstrated in [34] and a plug-and-measure device in [11].…”

“…The internal gate resistance on the chip has to be the dominant part of the resistance, and the parasitic resistance of, e.g., bond wires from the package pins to the die, has to be small for an excellent junction temperature measurement (R p << R Gi (T j )) [49]. This is typically the case for most internal gate resistors with a value greater than 1 Ω.…”

“…Based on this principle, the T J -R Gi -monitor has been designed as a measurement device, which can be installed between the gate driver and the DUT (see Fig. 4) [11]. During the measurement phase, the gate voltage is superimposed with a sinusoidal small voltage source u 1 with an amplitude of 600 mV.…”

“…An overview of TSEPs' sensitivity and applicability is given in [6]- [8]. Most of the TSEPs known for Si semiconductors have also been applied to SiC devices [9]- [19]. Transfer possibilities for GaN are currently being researched [17], [20]- [23].…”

“…The main part of the internal gate resistance normally consists of a polysilicon resistor, which is located on the semiconductor chip and has a positive temperature coefficient. The measurement of the internal gate resistance can be based on a superimposed high-frequency measurement signal on the gate voltage in either on-or offstate [11], [13], [34], [35], via DC gate current injection [36] or via measurement of the peak gate current [37], [38]. A calibration Another group of TSEPs is based on changes in the dynamic switching characteristic, which also depends on the temperature and the value of the internal gate resistance.…”