Experimental 0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique

Ohno, Takao; Kado, Yuichi; Harada, Masahiko; Tsuchiya, Toshiaki

doi:10.1109/16.398663

Cited by 86 publications

(18 citation statements)

References 8 publications

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“…Fully-depleted CMOS/SOI devices o er superior electrical characteristics over bulk CMOS devices (Ohno et al 1995) such as reduced junction capacitances, increased channel mobility, suppressed short-channel e ect, excellent latchup immunity, and improved subthreshold characteristics (Hsiao and Woo, 1995), and hence they are attracting much attention as potential candidates for high-performance VLSI/ULSI components to achieve higher packing density, faster speed and with a low voltage supply. As a consequency, submicrometre and deep-submicrometre SOI circuit design and simulation are becoming increasingly important in VLSI/ ULSI technology research.…”

Section: Introductionmentioning

confidence: 99%

Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation

Hu¹,

Jang²

1998

International Journal of Electronics

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A simple, complete, and analytical deep submicrometre SOI MOSFET model for accurate simulation of digital/analogue circuits is presented. The model was developed by using the drift-di usion equation with a modi® ed mobility formula to account for velocity overshoot, and was based on a quasi-two-dimensional Poisson' s equation. It is a charge control model, expressed as a function of inversion charge per unit area. The drain current equation has been successfully applied to model both submicron and deep-submicrometre SOI nMOSFETs with various channel lengths and a good agreement between the modelled and experimental data has been obtained. The model contains the following advanced features: (a) precise description of the subthreshold, near threshold, and above-threshold regions of operation, and I± V and G± V characteristics in the saturation region; (b) single-piece drain current equation smoothly continuous from the linear region to the saturation region; (c) consideration of the source/drain resistance; (d) inclusion of important short channel e ects such as velocity overshoot, drain induced barrier lowering and channel length modulation; (e) inclusion of the self-heating e ect due to the low thermal conductivity of the buried oxide; and (f) inclusion of the impact-ionization of MOS devices and the parasitic BJT e ect associated with drain breakdown. This model uses few ® tting parameters and can be employed in a circuit simulator to improve the convergence of simulation and computational e ciency. NomenclatureC of (C ob ) front (back) gate± oxide capacitance C d (C i, C gc ) 1-D depletion (inversion, gate-channel) capacitance E sf (E b ) front (back)-gate surface electric ® eld E y (E c ) electric (critical electric) ® eld I DS (I Dsat ) drain (saturation drain) current k B Boltzmann constant K d ( K ox ) slicon (gate oxide) thermal conductivity L(W) e ective channel length (width) N ch substrate concentration Q m inversion charge density Q mS Â (Q mD Â ) inversion charge density at the intrinsic source (drain) end q elementary charge R S ( R D ) source (drain) series resistance R th thermal resistance t si SOI ® lm thickness T l (T n ) lattice (electron) temperature U l (U n ) lattice (electron) thermal voltage V GF (V GB ) front (back) gate± source voltage V Ff (V Fb ) front (back)¯at-band voltage V T (D V T ) threshold voltage (threshold voltage reduction) V BI built-in potential of the source± substrate junction V GC gate channel voltage v c (v o c ) critical velocity (at ambient temperature) V CS (V CS Â ,VDS ) channel± source (channel± intrinsic source, drain± source) voltage ² s permittivity of silicon ¹ n (¹ o n ) non-local electron (low ® eld electron) mobility ¹ o (¹ so ) maximum low-® eld (at ambient temperature) mobilityx ,Lv,a µ ® tting constants y Sf ( y b ) front-gate (back-gate) surface potential

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Section: Introductionmentioning

confidence: 99%

Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation

Hu¹,

Jang²

1998

International Journal of Electronics

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“…These involve drastically reduced production cost and threading dislocations, improved device performance and thermal conductivity. For instance, it is reported that a thin BOX layer formed by low dose oxygen implantation is effective on reducing the self heating effect in metal-oxidesemiconductor field effect transistors [8]. However, as the implantation dose is reduced, the BOX layer tends to have discontinuities including breaks and high density of silicon islands.…”

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confidence: 99%

Investigation of silicon on insulator fabricated by two-step O+ implantation

Wei

Xue

et al. 2011

Chin. Sci. Bull.

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In this paper, we investigated the dose window of forming a continuous buried oxide (BOX) layer by single implantation at the implantation energy of 200 keV. Then, an improved two-step implantation process with second implantation dose of 3×10 15 cm −2 was developed to fabricate high quality separation by implanted oxygen (SIMOX) silicon on insulator (SOI) wafers. Compared with traditional single implantation, the implantation dose is reduced by 18.2%. In addition, the thickness and uniformity of the BOX layers were evaluated by spectroscopic ellipsometry. Defect-free top Si as well as atomic-scale sharp top Si/buried oxide interfaces were observed by transmission electron microscopy, indicating a high crystal quality and a perfect structure of the SOI fabricated by two step implantation. The top Si/BOX interface morphology of the SOI wafers fabricated by single or two-step implantation was also investigated by atomic force microscopy. silicon on insulator, interface morphology, dose window, separation by implanted oxygen Citation: Wei X, Xue Z Y, Wu A M, et al. Investigation of silicon on insulator fabricated by two-step O + implantation.Silicon-on-insulator wafers offer a number of advantages over bulk silicon wafers, such as high speed operation, low power consumption, anti-radiation, simple process and greater packaging densities. Now, it has been widely used in low-power/low-voltage and high-speed ultra-large-scale integrated (ULSI) circuits [1], micro-electro-mechanical system (MEMS) [2−4], high-voltage power devices [5] and optical waveguides [6]. Separation by implanted oxygen (SIMOX) is one of the leading techniques for synthesizing SOI wafers because it provides an excellent thickness uniformity of both the top Si and buried oxide (BOX) layers. Traditionally, the most widely used high dose SIMOX wafer is produced by implantation of more than 1.8×10 18 cm −2 16 O + at 550°C, which results in a BOX layer thickness of about 400 nm. However, the high dose implantation gives *Corresponding authors (rise not only to a high density of threading dislocations in the top Si layer, but also to a high production cost. In recent years, there has been a growing interest in low/medium-dose SIMOX (dose <1×10 18 cm −2 ) [7], with a BOX layer thickness of 50−200 nm, because of potential technological and economic advantages over high-dose SIMOX. These involve drastically reduced production cost and threading dislocations, improved device performance and thermal conductivity. For instance, it is reported that a thin BOX layer formed by low dose oxygen implantation is effective on reducing the self heating effect in metal-oxidesemiconductor field effect transistors [8]. However, as the implantation dose is reduced, the BOX layer tends to have discontinuities including breaks and high density of silicon islands. It is reported that Si islands are responsible for increased electrical leakage current through the BOX [9], or in extreme cases, its dielectric breakdown [10]. Many efforts

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“…Because the fully-depleted (FD) SOI device is fabricated on ultra-thin film SOI, it offers superior electrical characteristics over the bulk CMOS device [1] such as reduced junction capacitances, an increased channel mobility, a suppressed short-channel effect, and an excellent latchup immunity [2]. However, as dimensions of SOI CMOS devices are scaled down to the submicron regime, the source/drain (S/D) parasitic resistance becomes increasingly significant.…”

Section: Introductionmentioning

confidence: 99%

A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications

Park¹,

Oh²,

Kang³

et al. 2004

ETRI J

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Experimental 0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique

Cited by 86 publications

References 8 publications

Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation

Deep-submicrometre fully-depleted SOI MOSFET drain current model for digital/analogue circuit simulation

Investigation of silicon on insulator fabricated by two-step O+ implantation

A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications

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