Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion

Yesil, Soner; Sen, Cansu; Yılmaz, Ali Özgür

doi:10.1109/icecs46596.2019.8964743

Cited by 3 publications

(1 citation statement)

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“…Numerous approximation methods have been applied to nonlinear functions in the state-of-the-art to facilitate their deployment on an embedded device. The authors of [12,18,33] implemented a nonlinear function on an FPGA using a polynomial approximation technique, such as the piecewise linear (PWL) approximation method or the quadratic approximation technique. These methods require the use of adders and multipliers.…”

Section: Activation Functionsmentioning

confidence: 99%

An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

et al. 2021

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Convolutional Neural Networks (CNN) continue to dominate research in the area of hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its effectiveness in a variety of computer vision applications such as object segmentation, image classification, face detection, and traffic signs recognition, among others. However, there are numerous constraints for deploying CNNs on FPGA, including limited on-chip memory, CNN size, and configuration parameters. This paper introduces Ad-MobileNet, an advanced CNN model inspired by the baseline MobileNet model. The proposed model uses an Ad-depth engine, which is an improved version of the depth-wise separable convolution unit. Moreover, we propose an FPGA-based implementation model that supports the Mish, TanhExp, and ReLU activation functions. The experimental results using the CIFAR-10 dataset show that our Ad-MobileNet has a classification accuracy of 88.76% while requiring little computational hardware resources. Compared to state-of-the-art methods, our proposed method has a fairly high recognition rate while using fewer computational hardware resources. Indeed, the proposed model helps to reduce hardware resources by more than 41% compared to that of the baseline model.

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Section: Activation Functionsmentioning

confidence: 99%

An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

et al. 2021

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A Sparse Neural Network-Based Power Adaptive DPD Design and Its Hardware Implementation

2022

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In this paper, an efficient neural-network-based adaptive DPD design which performs well under power varying conditions is presented. The DPD design is derived on the basis of the envelop timedelay neural network (ETDNN). The redefined ETDNN-DPD requires the part of parameter updates, which enables to adapt it to the rapid change of power amplifier (PA) distortion. Additionally, the redefined ETDNN-DPD also maintains the stability of the compensation performances under varying power condition while its structure is pruned by the structured pruning. Furthermore, to verify its practical use, we also propose the weight scaling technique, which reduces multiplications of the redefined ETDNN-DPD, and applied it to the implementation of the redefined ETDNN-DPD on FPGA. Compared FPGA-implemented ETDNN-DPD with FPGA-implemented conventional memory polynomial DPD, we verified that our proposed DPD achieved 3.2 dB better error vector magnitude (EVM) while lower hardware resource utilization at the fixed power level. Moreover, our proposed DPD kept better performance under the varying power condition only by the partial update of its parameters than memory polynomial DPD.

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Hardware Implementation of Fixed-Point Convolutional Neural Network For Classification

Bouguezzi

Faiedh

Souani

2021

2021 IEEE International Conference on Design &Amp; Test of Integrated Micro &Amp; Nano-Systems (DTS)

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Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion

Cited by 3 publications

References 12 publications

An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

A Sparse Neural Network-Based Power Adaptive DPD Design and Its Hardware Implementation

Hardware Implementation of Fixed-Point Convolutional Neural Network For Classification

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