Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal–Oxide–Semiconductor Technology Including Its Distance Dependences

Ansari, Tania; Imafuku, Wataru; Yasuda, Masahiro; Mattausch, Hans Jürgen; Koide, Tetsushi

doi:10.7567/jjap.51.04de03

Cited by 2 publications

(1 citation statement)

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“…As both the WID random variation and RTN induced variation are statistical phenomena, large number of samples are required to characterize these variations. Conventionally, device-array based test structures, 18,24) or RO array based test structures 21,25) are used to characterize static variation. Various approaches are proposed to make the RO frequency sensitive to a particular variation source which helps to develop detailed statistical models of these variations.…”

Section: Introductionmentioning

confidence: 99%

Area-efficient reconfigurable ring oscillator for device and circuit level characterization of static and dynamic variations

Islam¹,

Onodera²

2014

Jpn. J. Appl. Phys.

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Accurate characterization of transistor variation under dynamic switching condition has become important for reliable digital circuit design. This paper proposes a reconfigurable ring oscillator (RO) structure which enables measurement of transistor level variation. Each inverter stage in the RO can be configured into several delay modes. The delay of a particular inverting stage can be made dominant by configuring an inhomogeneous RO structure. By scanning the inhomogeneous stage, delay variation of each stage can be measured. Furthermore, pMOSFET and nMOSFET variation can be measured separately by making only rise or fall delay dominant. Specific transistor with random telegraph noise (RTN) in the inhomogeneous stage can be identified by reconfiguring the inhomogeneous stage. Thus, using a single RO, static delay variation as well as dynamic variation such as RTN can be measured. The area for a 127-staged reconfigurable RO including peripheral circuits is only 0.0085 mm2 thus area-efficient measurement becomes possible. Measurement results from a 65-nm test chip shows the validity of the proposed circuit structure.

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