Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Zhao, Dan; Lee, Choong Hyun; Nishimura, Takuya; Nagashio, Kosuke; Cheng, Guo An; Toriumi, Akira

doi:10.7567/jjap.51.04da03

Cited by 21 publications

(13 citation statements)

References 26 publications

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“…The fin width ( W fin ) is used for the channel concentration of 8 × 10 19 cm − 3 which is extracted using the van der Pauw method on a blanket Ge epi layer on SOI. Note that the channel controllability decreases with increasing channel concentration and increasing W fin [ 12 , 13 ]. The large channel concentration requires the small W fin to maintain the low SS.…”

Section: Resultsmentioning

confidence: 99%

“…However, in the case of highly doped JL-FETs, the carriers undergo significant impurity scattering, owing to which the drive current is significantly degraded [ 7 ]. Furthermore, JL-FETs have the advantages of being simple to fabricate and have high charge mobility and low gate capacitance, in contrast to INV devices [ 8 – 12 ]. Recently, double-gate [ 13 ] and body-tied tri-gate [ 14 ] Ge JL-FET pMOSFETs were demonstrated on germanium-on-insulator substrates and bulk Si, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

2018

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During the formation of Ge fin structures on a silicon-on-insulator (SOI) substrate, we found that the dry etching process must be carefully controlled. Otherwise, it may lead to Ge over-etching or the formation of an undesirable Ge fin profile. If the etching process is not well controlled, the top Ge/SOI structure is etched away, and only the Si fin layer remains. In this case, the device exhibits abnormal characteristics. The etching process is emerging as a critical step in device scaling and packaging and affects attempts to increase the packing density and improve device performance. Therefore, it is suggested that optimization of operating the plasma reactor be performed through simulations, in order to not only adjust the process parameters used but also to modify the hardware employed. We are going to develop Ge junction-less devices by employing updated fabrication parameters. Besides, we want to eliminate misfit dislocations at the interface or to reduce threading dislocations by applying cyclic thermal annealing process to meet the goal of obtaining suspended structure of epitaxial Ge layers with high quality.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

2018

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“…The JL FET is promising for advanced nanoscale CMOS technology, possessing many advantages over conventional MOSFET such as simplicity, improved short-channel effects, and relaxed mobility degradation. 35 However, its drawback has been the degradation of S/D contact resistance because it has a lower S/ D doping level than conventional MOSFET. Fortunately, adopting the proposed M−I−S structure in the S/D region easily solves this problem without the need to increase S/D doping level.…”

Section: Resultsmentioning

confidence: 99%

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO₂/GeO₂ Interlayer Stack

Kim¹,

Kim²,

Kim³

et al. 2016

ACS Appl. Mater. Interfaces

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A perfect ohmic contact formation technique for low-resistance source/drain (S/D) contact of germanium (Ge) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed. A metal-interlayer-semiconductor (M-I-S) structure with an ultrathin TiO/GeO interlayer stack is introduced into the contact scheme to alleviate Fermi-level pinning (FLP), and reduce the electron Schottky barrier height (SBH). The TiO interlayer can alleviate FLP by preventing formation of metal-induced gap states (MIGS) with its very low tunneling resistance and series resistance and can provide very small electron energy barrier at the metal/TiO interface. The GeO layer can induce further alleviation of FLP by reducing interface state density (D) on Ge which is one of main causes of FLP. Moreover, the proposed TiO/GeO stack can minimize interface dipole formation which induces the SBH increase. The M-I-S structure incorporating the TiO/GeO interlayer stack achieves a perfect ohmic characteristic, which has proved unattainable with a single interlayer. FLP can be perfectly alleviated, and the SBH of the metal/n-Ge can be tremendously reduced. The proposed structure (Ti/TiO/GeO/n-Ge) exhibits 0.193 eV of effective electron SBH which achieves 0.36 eV of SBH reduction from that of the Ti/n-Ge structure. The proposed M-I-S structure can be suggested as a promising S/D contact technique for nanoscale Ge n-channel transistors to overcome the large electron SBH problem caused by severe FLP.

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“…The devices show similar current-voltage (I-V) characteristics to conventional FETs, and their on/off current ratio is larger than 10 4 . The fi eld-effect mobility is equal to 120 cm 2 /Vs and is independent of the channel carrier density (Zhao et al, 2011(Zhao et al, , 2012. N-channel germanium MOSFETs are notoriously diffi cult to fabricate and show poor performance despite the high mobility of electrons in bulk germanium.…”

Section: Germanium-on-insulator Devicesmentioning

confidence: 99%

Silicon-on-insulator (SOI) junctionless transistors

Colinge

2014

Silicon-on-Insulator (SOI) Technology

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Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Cited by 21 publications

References 26 publications

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO₂/GeO₂ Interlayer Stack

Silicon-on-insulator (SOI) junctionless transistors

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Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Cited by 21 publications

References 26 publications

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Effects of Etching Variations on Ge/Si Channel Formation and Device Performance

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack

Silicon-on-insulator (SOI) junctionless transistors

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Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO₂/GeO₂ Interlayer Stack