Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Tsormpatzoglou, A.; Dimitriadis, C. A.; Mouis, M.; Ghibaudo, G.; Collaert, N.

doi:10.1016/j.sse.2009.01.008

Cited by 22 publications

(14 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This is attributed to the GIDL effect as a consequence of the electrons tunneling assisted by the interface states in the gate overlap regions. 9,10 In order to complete this analysis, a good agreement is obtained in Figure 7 when we compare the transfer measured characteristics and those modeled for FinFETs with HfSi x O y / SiO 2 gate stack. This is accomplished by adding the results of the SDDGM model and appropriately including the contributions of I GIDL and I Ggen .…”

Section: A Gate Current Modelingmentioning

confidence: 73%

“…7,8 The leakage current due to gate-induced drain leakage (GIDL) effect in the gate-to-drain overlap region and its contribution to drain current (I D ) is another important issue. [9][10][11][12][13] With the exception of Ref. 13, the presence of I G in the subthreshold region is usually neglected, because its magnitude and impact on I D were lower than those due to GIDL current (I GIDL ).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Garduno¹,

Cerdeira

Estrada

et al. 2013

Journal of Applied Physics

View full text Add to dashboard Cite

Articles you may be interested inModel of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors J. Appl. Phys. 109, 084524 (2011); 10.1063/1.3575324 Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device J. Appl. Phys. 109, 084504 (2011); 10.1063/1.3553836Modeling of spin metal-oxide-semiconductor field-effect transistor: A nonequilibrium Green's function approach with spin relaxation J. Appl. Phys.Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorRecently, we developed a symmetric doped double gate model for MOSFETs, which includes a direct tunneling model for gate current considering its dependence on the voltages applied to the gate and drain electrodes. Since different tunneling mechanisms can dominate the gate and drain/ source leakage currents depending on the transistor operation regime, the gate stack dimensions and the insulating materials used as gate dielectric, in this work, we analyze and model specific features of such currents in SOI FinFET devices. We present an analytical model which takes into account three main conduction mechanisms of leakage currents associated with the gate structure and is valid for a wide operation range. An improved model to describe the behavior of direct tunneling is proposed to avoid the use of fitting parameters. It is shown that carriers tunneling assisted by trap states in the dielectric material of the overlap regions should be considered, as it can become predominant in the subthreshold regime. Moreover, a band-to-band tunneling model is included because of its large impact on the drain leakage current. The present improved model for gate leakage currents is validated by experimental results obtained on FinFETs with different dimensions, gate dielectric materials and performed under different bias conditions. V C 2013 American Institute of Physics. [http://dx.

show abstract

Section: A Gate Current Modelingmentioning

confidence: 73%

Section: Introductionmentioning

confidence: 99%

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Garduno¹,

Cerdeira

Estrada

et al. 2013

Journal of Applied Physics

View full text Add to dashboard Cite

show abstract

“…As the ESDG MOSFET is not fabricated yet, thus, in order to validate the simulated results, proposed device is first calibrated with experimental results of DG [12] at 60nm channel length as shown in Fig. 1(c).…”

Section: Device Specificationsmentioning

confidence: 99%

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

Kumari¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP 2 and VIP 3 . The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

show abstract

“…Effect of I G and I GIDL in total gate and drain currents Figures 3(a) and 3(b) show measured gate and source current (I S ) and modeled I G and I GIDL . 5,6,24 In the following figures, drain to source current is calculated using the SDDGM, complemented by the modeled gate tunneling currents and GIDL current. Furthermore it is seen that I S is well reproduced by considering the GIDL effect for both channel lengths in the voltage region below -0.1 V. This is because BBT becomes more important as V DG overcomes FIG.…”

Section: A Direct Tunneling Current Modeling On Finfetsmentioning

confidence: 99%

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

Garduno

Cerdeira

Estrada

et al. 2011

Journal of Applied Physics

View full text Add to dashboard Cite

Articles you may be interested inImproved modeling of gate leakage currents for fin-shaped field-effect transistors J. Appl. Phys. 113, 124507 (2013); 10.1063/1.4795403 Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal-oxide-semiconductor field-effect transistors Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors J. Appl. Phys. 92, 937 (2002); 10.1063/1.1486022Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorThe contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed. In order to fulfill this task, expressions for the leakage current due to carrier tunneling and GIDL effects at a Metal-Dielectric-Semiconductor structure were established and incorporated in the Symmetric Doped Double-Gate Model (SDDGM) for metal-oxide-semiconductor field-effect transistors (MOSFET). It is shown that both phenomena have to be taken into account for precise modeling of the device in all the operation regions although GIDL current can become predominant in the subthreshold region. The dependence of gate tunneling current in inversion and subthreshold regimes of operation is modeled as function of the applied voltages and transistor physical parameters by using analytical expressions. The present leakage current model is validated by comparing modeled with measured total gate and drain currents for FinFETs with different dimensions.

show abstract

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

Cited by 22 publications

References 19 publications

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Improved modeling of gate leakage currents for fin–shaped field–effect transistors

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

Contact Info

Product

Resources

About