Experimental demonstration of single electron transistors featuring SiO2 plasma-enhanced atomic layer deposition in Ni-SiO2-Ni tunnel junctions

Abstract

We report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultra-thin (≈1 nm) tunnel-transparent SiO2 in Ni-SiO2-Ni tunnel junctions. We show that as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni-SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultra-thin barriers. Using this technique, we successfully

Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

“…Likewise, substituting palladium for nickel on the top layer (Ni-SiO2-Pd) shows behavior indicative of the top palladium layer oxidizing at the metal-SiO2 interface but unlike Al2O3, this oxide can be reduced. These experiments suggest that the oxidation of the top metal layer is unavoidable (at least for oxide dielectrics such as Al2O3 and SiO2) and that reducing the NiO at the This is consistent with hydrogen-promoted reduction of the parasitic NiO to Ni: H 2 + NiO = H 2 O + Ni; the H 2 O is removed during annealing [11,38]. Further measurements of cross-tie devices by TEM and EDX revealed that in addition to the oxide formation on the bottom Ni layer, the top Ni electrodes, deposited on the PEALD SiO 2 , are likewise oxidized and that a second annealing step is required to reduce the parasitic NiO at the lower interface of the top Ni layer [11].…”

“…Fortunately, NiO can be reduced to Ni by annealing in hydrogen at moderately high temperatures ≥300 °C [35][36][37]. We have found that a forming gas anneal (FGA) at 400 °C for 2 min in 5% H2-95% Ar causes the conductance of the cross-tie structures with two cycles of PEALD SiO2 to increase from G ≈ 5 nS to G > 600 μS [11], while a 30 min FGA is required to increase the conductance of the Ni nanowire covered by ~1 nm of SiO2 back to that of the as-deposited nanowires [11,38]. This is consistent with hydrogen-promoted reduction of the parasitic NiO to Ni: H2 + NiO = H2O + Ni; the H2O is removed during annealing [11,38].…”

“…A modification of this process, known as "half damascene" fabrication, is used to decrease the overlap of the source and drain with the island by fabricating an island inlaid in the substrate dielectric ( Figure 2) [11]. This lowers the capacitance of the junctions by narrowing the width of the island and avoiding the side overlap always present in cross-tie design and thus raises the maximum operating temperature of the device.…”

“…We have found that a forming gas anneal (FGA) at 400 °C for 2 min in 5% H2-95% Ar causes the conductance of the cross-tie structures with two cycles of PEALD SiO2 to increase from G ≈ 5 nS to G > 600 μS [11], while a 30 min FGA is required to increase the conductance of the Ni nanowire covered by ~1 nm of SiO2 back to that of the as-deposited nanowires [11,38]. This is consistent with hydrogen-promoted reduction of the parasitic NiO to Ni: H2 + NiO = H2O + Ni; the H2O is removed during annealing [11,38]. Further measurements of cross-tie devices by TEM and EDX revealed that in addition to the oxide formation on the bottom Ni layer, the top Ni electrodes, deposited on the PEALD SiO2, are likewise oxidized and that a second annealing step is required to reduce the parasitic NiO at the lower interface of the top Ni layer [11].…”

“…The thickness of the barrier is estimated using the known deposition rate for the ALD process and has been validated by transmission electron microscopy (TEM, FEI, Hillsboro, OR, USA) [11,14]. In order for the electron wave function to be localized to the island the junction resistance R J must satisfy the following condition: R J > R Q [10] (where R Q = h/e 2 is the quantum resistance, h is Planck's constant, and e is the elementary charge).…”