Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs

Exploiting multiple functionality for nano-scale reconfigurable systems

“…The transfer curves demonstrate how the inverter's switching point changes with back-gate bias. These curves are similar in general form to the characteristics of the planar "ground plane" (GP) CMOS inverter described by Ieong et al [20], and match fairly closely the relationship between the back gate (V G2 ) bias and the shift in switching point observed in their devices. The basic mechanism can be extended to create more complex logic circuits.…”

“…As a result, it becomes possible to strongly shift the threshold voltage of either gate by changing the bias level on the other gate -an effect that is somewhat analogous to that in EEPROM devices in which charge on a floating gate alters the effective threshold of the transistor seen at the control gate. This has been previously reported in both HEMT [6] and CMOS [20] technologies, and is illustrated in Figure 2 for a simulated device using a double gate FDSOI nMOSFET model [14] loosely based on the idealized SOI double-gate device described by Ren et al [38]. Figure 3 shows the DC transfer characteristics of an inverter circuit formed from these DG transistors in which the two back gate connections are tied together such that the threshold voltages of the p and n-type transistors shift in opposite directions for a given change in bias.…”

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

“…In bulk MOSFETs, high surface electric field was found in the heavily doped channel (for controlling the shortchannel effects). For comparison, it was found that the effective field in undoped double gate channel is 0.5 MV/ cm which is half of that in a normal bulk MOSFET [30]. However, even with lightly doped or undoped channel, the electron mobility degradation for channel thickness below 20 nm may be clearly observed at a low inversion carrier density (10 12 cm À2 ), due to phonon scattering in the thin confined channel [31].…”

SRAM Read/Write Margin Enhancements Using FinFETs

“…2) Pass-Gate Feedback (PGFB): Whereas adaptive body biasing becomes less effective with bulk-Si MOSFET scaling, back-gate (BG) biasing of a thin-body MOSFET remains effective for dynamic control of with transistor scaling, and can provide improved control of short-channel effects as well [38]. The strong BG biasing effect can thus be leveraged [39] to optimize the performance of FinFET-based SRAMs through a dynamic adjustment of the effective cell -ratio.…”