Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits

Coudrain, P.; Souare, Papa Momar; Prieto, R.; Fiori, Vincent; Farcy, A.; Pailleur, L. Le; Colonna, Jean-Philippe; Santos, Carla Eliete Iochims dos; Vivet, Pascal; Ben-Jamaa, Haykel; Dutoit, Denis; Crecy, F. de; Dumas, S.; Chancel, C.; Lattard, Didier; Chéramy, S.

doi:10.1109/mdat.2015.2506678

Cited by 16 publications

(11 citation statements)

References 19 publications

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“…The power model used for thermal simulation includes both dynamic power and leakage power. The dynamic power model from [15] was used for the voltage scaling and can be obtained using (2). In the equation, α is the application power ratio, C is the dynamic capacitance, V dd is the operating voltage and f is the operating frequency.…”

Section: D-mcp Models and Prior Workmentioning

confidence: 99%

“…shorter interconnect delays and better performances [1]. However, 3D multi‐core processors (3D‐MCPs) are more likely to exhibit severe thermal problems due to their high‐power density and lack of heat dissipation paths [2, 3]. For example, the peak temperature of a 3D two‐layer eight‐CP may be

20^{\circ} normalC

higher than that of a 2D eight‐CP [4].…”

Section: Introductionmentioning

confidence: 99%

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Online task scheduler in 3D‐MCPs with TADVA

Liao

Wen²

2018

IET Computers & Digital Techniques

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Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and highperformance operating modes. The proposed DVA strategies can be employed in online, thermally constrained task schedulers. Three DVA strategies, random DVA, thermal-aware DVA (TADVA) and TADVA2.0, are proposed to reduce the temperature increase in 3D-MCPs by pre-emptively and dynamically estimating the optimum VAs for all cores in the processor during runtime once the chip begins operating. In particular, TADVA2.0 uses the temperature-variation rates of the cores and takes into account two important thermal behaviours of 3D-MCPs that can effectively limit the temperature increase in 3D-MCPs. Experimental results indicate that, when compared with two previous online thermally constrained task schedulers, the proposed task scheduler with their novel DVA strategy can reduce hotspot occurrences by ∼60% and improve throughput by ∼8%. These results indicate that the proposed TADVA2.0 strategy is an effective technique for suppressing hotspot occurrences and optimising throughput for 3D-MCPs subject to thermal constraints.

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Section: D-mcp Models and Prior Workmentioning

confidence: 99%

20^{\circ} normalC

higher than that of a 2D eight‐CP [4].…”

Section: Introductionmentioning

confidence: 99%

Online task scheduler in 3D‐MCPs with TADVA

Liao

Wen²

2018

IET Computers & Digital Techniques

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“…Consequently, the integration significantly increases the power density of the processor. Therefore, these high-density processors (packaged with stacked memory) face even more severe thermal issues than low-density 2D processors [15]. Promising as they are, the thermal issues associated with high-density processors prevent them from going mainstream.…”

Section: Introductionmentioning

confidence: 99%

“…CoMeT enables users to evaluate and analyze run-time thermal management policies for various core-memory (integration) configurations as shown in Figure 1 [15,20,36,39,49,51]. Figure 1(a) shows a conventional but the most common configuration with cores and 2D DRAM on separate packages.…”

Section: Introductionmentioning

confidence: 99%

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

Siddhu¹,

Kedia²,

Pandey³

et al. 2021

Preprint

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Processing cores and the accompanying main memory working in tandem enable the modern processors. Dissipating heat produced from computation remains a significant problem for processors. Therefore, the thermal management of processors continues to be an active subject of research. Most thermal management research takes place using simulations, given the challenges involved in measuring temperatures in real processors. Fast yet accurate interval thermal simulation toolchains remain the research tool of choice to study thermal management in processors at system-level. However, since in most existing processors, core and memory are fabricated on separate packages, with the memory having lower power densities than the cores, thermal management research in processors primarily focused on the cores. Consequently, state-of-the-art interval thermal simulation toolchains remain limited to core-only simulations.The memory bandwidth limitations associated with 2D processors lead to high-density 2.5D and 3D packaging technology. 2.5D packaging technology places cores and memory on the same package. 3D packaging technology takes it further by stacking layers of memory on the top of cores themselves. These new packagings significantly increase the power density of the processors, making them prone to overheating. Therefore, mitigating thermal issues in high-density processors (packaged with stacked memory) becomes an even more pressing problem. However, given the lack of thermal modeling for memories in existing interval thermal simulation toolchains, they are unsuitable for studying thermal management for high-density processors.To address this issue, we present CoMeT , the first integrated Core and Memory interval Thermal simulation toolchain. CoMeT comprehensively supports thermal simulation of high-and low-density processors corresponding to four different core-memory (integration) configurations -off-chip DDR memory, off-chip 3D memory, 2.5D, and 3D. CoMeT supports several novel features that facilitate overlying system research. Compared to an equivalent state-of-the-art core-only toolchain, CoMeT adds only an additional ∼5% simulation-time overhead. The source code of CoMeT has been made open for public use under the MIT license.

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“…The reliability has not been fully studied and guaranteed [12]. Identifying defects and analyzing the failure mechanism play important roles in the optimization and improvement of the design, production, and use of TSV 3D integrated devices [13][14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

Yuan¹,

Zhang²,

Xia³

et al. 2019

IJPE

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TSV technology can achieve heterogeneous integration by stacking different technologies and functions of logic chip, memory, MEMS, etc., as a system. There are many significant advantages for heterogeneous integration in terms of cost, performance, and time to market. TSV technology has the potential to improve 3D packaging. As the important physical connection and electrical connection between the chips, TSV's reliability is undoubtedly the key to determine the reliability of TSV three-dimensional integrated devices. As a new interconnect technology, TSV technology faces many process difficulties and challenges. Its reliability has not been fully studied and guaranteed. The process optimization and reliability improvement of TSV have become a hot topic in recent years. Recognition process defects and analysis of the failure mechanism play important roles in the optimization and improvement of design, production, and use of TSV three-dimensional integrated devices. In this paper, the square TSV and circular TSV with different ratios were researched by microphysical analysis and data analysis. The analysis results revealed the key technological factors and physical mechanism of formation of the TSV defects, which can support TSV device development, production, and reliable application.

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Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits

Cited by 16 publications

References 19 publications

Online task scheduler in 3D‐MCPs with TADVA

Online task scheduler in 3D‐MCPs with TADVA

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems

Boundary Layers Defect Diagnosis and Analysis of Through Silicon Via (TSV)

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