3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes ( C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.Index Terms-Low temperature process, molecular bonding, solid phase epitaxy, three-dimensional (3-D) integration, 3-D monolithic integration, 3-D sequential integration.

Abstract-

3D VLSI with a CoolCube TM integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm². This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube TM technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization. I-INTRODUCTION: 3D-VLSI sequential processing of stacked devices offers a 3D contact pitch equal to planar contacted gate pitch. Moreover, thanks to the lithography alignment precision depending only on the stacked technology node, the via density reaches 10 8 vias/mm 2 with a 90nm-CPP technology. This 3D contact pitch allows fully leveraging the 3 rd dimension with negligible area penalty due to 3D via or landing pad size compared to packaging solutions as shown in Fig.1 [1] .3DVLSI motivations-Actually, scaling below the 28 nm technology node does not yield substantial cost reductions [2] . Among scaling challenges, the increasing interconnect delay overshadows benefits stemming from costly transistor scaling. 3D VLSI interest has been demonstrated via a Power-Performance-Area benchmark for FPGA applications stacking two layers of 14nm FDSOI technology with W/SiO2 interconnect in between [3] . Dramatic area and Energy Delay Product (EDP) reduction is achieved, with benefits exceeding those of downscaling to the 10 nm node (Figs.2&3). 3DVLSI partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. In parallel, partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [6,7] ) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III-V nFETs above SiGe pFETs [8,9] . These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI partitioning at the transistor level allows performance gain as it facilitates the cointegration of high performance n&p-FETs compared to a coplanar scheme. Finally, 3DVLSI, with its high contact density, is also anticipated as a powerful solution for heterogeneous cointegrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [10, 11] or highly miniaturized imagers [12] . Fig.4 summarizes the three main integration schemes foreseen for ...

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