Experimental study and analysis of soft errors in 90nm Xilinx FPGA and beyond

Lesea, A.; Castellani-Coulie, K.

doi:10.1109/radecs.2007.5205556

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…that is, the average number of failures (e.g., number of memory upsets) that occur within one billion hours of operation [4]. However, not all radiation effects cause an observable error or a system crash in an MPSoC application [14]. For example, a configuration upset in an unused Look Up Table (LUT) of the PL will probably not affect the operation of a hardware accelerator [15].…”

Section: A Amd 16nm Finfet Xczu9eg Mpsocmentioning

confidence: 99%

“…However, using the same device at 60 deg latitude and 40k feet altitude will increase the upset rate of the memories to one upset per 1.8 months. As mentioned, not all upsets will lead to an error since practical designs commonly do not utilise 100% of their resources, and some upsets are logically masked during circuit operation [7], [14], [15]. Nevertheless, given the tens of thousands of flights per day, the possibility of an SRAM cell upset impacting the safety of a flight is high if the necessary soft error mitigation schemes on the MPSoC design are not in place.…”

Section: Neutron-induced Failures In Mpsoc-based Terrestrial Applicat...mentioning

confidence: 99%

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Evaluation of the Xilinx Deep Learning Processing Unit under Neutron Irradiation

Agiakatsikas

Foutris

Sari

et al. 2021

2021 21th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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The AMD UltraScale+ XCZU9EG device is a Multi-Processor System-on-Chip (MPSoC) with embedded Programmable Logic (PL) that excels in many Edge (e.g., automotive or avionics) and Cloud (e.g., data centres) terrestrial applications. However, it incorporates a large amount of SRAM cells, making the device vulnerable to Neutron-induced Single Event Upsets (NSEUs) or otherwise soft errors. Semiconductor vendors incorporate soft error mitigation mechanisms to recover memory upsets (i.e., faults) before they propagate to the application output and become an error. But how effective are the MPSoC's mitigation schemes? Can they effectively recover upsets in high altitude or large scale applications under different workloads? This article answers the above research questions through a solid study that entails accelerated neutron radiation testing and dependability analysis. We test the device on a broad range of workloads, like multi-threaded software used for pose estimation and weather prediction or a software/hardware (SW/HW) codesign image classification application running on the AMD Deep Learning Processing Unit (DPU). Assuming a one-node MPSoC system in New York City (NYC) at 40k feet, all tested software applications achieve a Mean Time To Failure (MTTF) greater than 148 months, which shows that upsets are effectively recovered in the processing system of the MPSoC. However, the SW/HW co-design (i.e., DPU) in the same one-node system at 40k feet has an MTTF = 4 months due to the high failure rate of its PL accelerator, which emphasises that some MPSoC workloads may require additional NSEU mitigation schemes. Nevertheless, we show that the MTTF of the DPU can increase to 87 months without any overhead if one disregards the failure rate of tolerable errors since they do not affect the correctness of the classification output.

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Section: A Amd 16nm Finfet Xczu9eg Mpsocmentioning

confidence: 99%