Experimental study of a surfactant-assisted SiGe graded layer and a symmetrically strained Si/Ge superlattice for thermoelectric applications

Anisotropic Thermal Conductivity of Ge Quantum-Dot and Symmetrically Strained Si/Ge Superlattices

“…To obtain the symmetrically strained Si/Ge superlattice, a SiGe alloy buffer layer was grown rst to accommodate the lattice mismatch between the Si and the Ge. The buffer part of JL215, prepared by a surfactant mediation technique, 27 consists of a 500 Å Si layer, followed by a 1 m continuously graded Si 1ƒx Ge x alloy layer with x increasing from 0 to 0.5, and a 0 3 m Si 0 5 Ge 0 5 alloy layer. The superlattice part, a 300-period Si(20 Å)/Ge(20 Å) layer, was grown at 350 :C and doped to about 1 10 19 cm ƒ3 using Sb as a dopant.…”

Low-Temperature and Metamorphic Buffer Layers

“…Buffer layers with linearly-graded composition, and therefore lattice constant, have been extensively investigated in a number of material systems, including In x Ga 1Àx As/GaAs [25,26,51,[96][97][98][99][100][101][102][103][104], In x Al 1Àx As/GaAs [34,75,103,[105][106][107][108][109][110], In x Al y Ga 1ÀxÀy As/GaAs [18,19,23,35,80,95,111], Si 1Àx Ge x /Si [112][113][114][115][116], In x Ga 1Àx P/GaAs [117][118][119], In x Ga 1Àx P/ GaP [120], ZnS y Se 1Ày /GaAs [102,121], and In x Ga 1Àx Sb/GaSb [122,123]. A possible advantage of continuous grading is that layer-by-layer growth may be maintained without the intrusion of island growth associated with large, abrupt changes in composition [119].…”

Comparison of Nonlinear Grading Approaches for ZnSSe/GaAs (001) Heterostructrures

“…The realization of semiconductor devices on a lattice-mismatched substrate is typically achieved by metamorphic (partly-relaxed) growth (1)(2)(3)(4)(5)(6), which is accompanied by elastic strains and threading dislocation defects (7). Compositionally-graded buffer layers are commonly employed to accommodate the lattice mismatch (8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23)(24)(25)(26), with the goal of reducing the density of threading dislocations and, in some cases, with the added goal of controlling the residual strain. Use of such buffer layers increases the complexity and cost of the device processing, so it is desirable to maximize the effectiveness of the buffer layer with the minimum requirement on thickness.…”