Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O’uchi, S.; Tsukada, Junichi; Yamauchi, H.; Ishikawa, Yoshihiro; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

doi:10.7567/jjap.53.04ed16

Cited by 4 publications

(4 citation statements)

References 45 publications

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“…32,33) Recently, we have developed FG-type and charge-trapping (CT)-type FinFET flash memories, and confirmed that the TG structure has a larger memory window and a higher SCE immunity than the DG structure owing to the additional top gate and recessed buried oxide (BOX) region. [34][35][36][37] Moreover, we have also demonstrated FG-type split-gate FinFET flash memories with highly suppressed overerase and experimentally confirmed that nanosize triangular cross-sectional tunnel areas are useful for the fabrication of low-operating-voltage flash memories. 38,39) However, the fin channel shape and interpoly dielectric (IPD) material effects on the electrical characteristics of FG-type SOI-FinFET flash memories have not been investigated sufficiently, although high-k dielectric stacks and barrier-engineered multilayers have been used as an IPD layer for improving the gate coupling of the conventional bulk planar FG-type flash memories.…”

Section: Introductionsupporting

confidence: 56%

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Liu

Nabatame

Nguyen

et al. 2015

Jpn. J. Appl. Phys.

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Floating-gate (FG)-type three-dimensional (3D) fin channel flash memories with triangular fin (TF) and rectangular fin (RF) channels and different interpoly dielectric (IPD) materials have been successfully fabricated using (100)- and (110)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The electrical characteristics of the fabricated FG-type 3D fin channel flash memories including threshold voltage (Vt) variability, program/erase (P/E) speed, memory window, endurance, and data retention at room temperature and 85 °C have been comparatively investigated. A higher P/E speed, a larger memory window, and a lower-voltage operation are experimentally obtained in the TF channel flash memories with an Al2O3–nitride–oxide (ANO) IPD layer (TF-ANO) than in the RF channel ones with the same ANO IPD layer (RF-ANO) and the TF channel ones with an oxide–nitride–oxide (ONO) IPD layer (TF-ONO). The larger memory window and lower-voltage operation of TF-ANO flash memories are due to the high-k effect of the Al2O3 layer and the electric field enhancement at the sharp foot edges of the TF channels. It was also found that data retention for all fabricated FG-type 3D fin channel flash memories shows a weak dependence on temperature.

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Section: Introductionsupporting

confidence: 56%

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Liu

Nabatame

Nguyen

et al. 2015

Jpn. J. Appl. Phys.

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“…from the pioneer work on graphene NVM device, [27] which is similar to the hysteresis measurement. In the Si based memory research field, [26,28,29] on the other hand, the memory window is determined from high and low V th s, which are measured after program or erase (P/E) operation. That is, the P/E operation is conducted by applying the pulse voltage to the control gate.…”

mentioning

confidence: 99%

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

Sasaki

Ueno

Taniguchi

et al. 2020

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In recent years, 2D materials including semimetallic graphene, semiconducting transition metal dichalcogenides (TMDs) and insulating h-BN have emerged as potential next generation electronic materials. For instance, semiconducting TMDs have been studied as channels in field effect transistors The memory window of floating gate (FG) type non-volatile memory (NVM) devices is a fundamental figure of merit used not only to evaluate the performance, such as retention and endurance, but also to discuss the feasibility of advanced functional memory devices. However, the memory window of 2D materials based NVM devices is historically determined from round sweep transfer curves, while that of conventional Si NVM devices is determined from high and low threshold voltages (V th s), which are measured by single sweep transfer curves. Here, it is elucidated that the memory window of 2D NVM devices determined from round sweep transfer curves is overestimated compared with that determined from single sweep transfer curves. The floating gate voltage measurement proposed in this study clarifies that the V th s in round sweep are controlled not only by the number of charges stored in floating gate but also by capacitive coupling between floating gate and back gate. The present finding on the overestimation of memory window enables to appropriately evaluate the potential of 2D NVM devices. (FETs), since their atomically thin nature can suppress the short channel effects that scaled Si-FETs have faced. [1-3] Not only n-MoS 2 FETs [4,5] but also ambipolar WSe 2 or MoTe 2 FETs [6-8] have been widely investigated from the context of channel mobility, contact engineering, etc. In addition, to explore their intrinsic properties due to the dangling bond free interface, 2D hetero-stack technology enables the fabrication of more advanced device structure [9] where insulating h-BN is applied as the atomically flat substrate [10,11] and gate insulator [12,13] with SiO 2 compatible permittivity (2-4). [14] As well as FETs, 2D materials have been utilized in non-volatile memory (NVM) devices, which are one of key building blocks for modern integrated circuits. [15,16] In particular, lots of efforts have been devoted to floating gate (FG) type memory devices. Their device structures have also evolved from the early stage of MoS 2 channel/HfO 2 tunnel barrier/multilayer graphene FG [17] stacks to recent 2D hetero-stack of WS 2 channel/h-BN tunnel barrier/graphite FG, [18] where the large memory window over 20 V for gate voltage (V G) range of ± 25 V and a good retention characteristic of 13% charge loss after 10 years have been demonstrated. Interestingly, many other 2D NVM devices, such as black phosphorus channel device and so on, [19-22] have also exhibited the large memory window, regardless of material systems, even though the origin has rarely been discussed. Moreover, 2D hetero-stacks have recently been further extended to artificial synaptic emulators for neuromorphic computing. [23] As mentioned above, the memory window, which is defined...

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“…This may be attributed to the thinner h -BN of device 3 (14.0 nm) than device 2 (19.1 nm) and not the interface quality. Moreover, the trends of memory window opening of devices 2 and 3 are much better than that of Si flash memory, in which the memory window opens quite slowly with increasing pulse width. ,,− Although the comparison between the present 2D heterostructured NVM and Si flash memory may not be fair since there are some differences, such as back gate/top gate structures and single-cell level/array level benchmarks, the improved memory window opening trends clearly represent the inherently high potential of ultrafast operation in 2D heterostructured NVMs.…”

Section: Resultsmentioning

confidence: 85%

Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength ofh-BN

Sasaki

Ueno

Taniguchi

et al. 2022

ACS Appl. Mater. Interfaces

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Recently, the ultrafast operation (∼20 ns) of a two-dimensional (2D) heterostructured nonvolatile memory (NVM) device was demonstrated, attracting considerable attention. However, there is no consensus on its physical origin. In this study, various 2D NVM device structures are compared. First, we reveal that the hole injection at the metal/MoS2 interface is the speed-limiting path in the NVM device with the access region. Therefore, MoS2 NVM devices with a direct tunneling path between source/drain electrodes and the floating gate are fabricated by removing the access region. Indeed, a 50 ns program/erase operation is successfully achieved for devices with metal source/drain electrodes as well as graphite source/drain electrodes. This controlled experiment proves that an atomically sharp interface is not necessary for ultrafast operation, which is contrary to the previous literature. Finally, the dielectric breakdown strength (E BD) of h-BN under short voltage pulses is examined. Since a high dielectric breakdown strength allows a large tunneling current, ultrafast operations can be achieved. Surprisingly, an E BD = 26.1 MV/cm for h-BN is realized under short voltage pulses, largely exceeding the E BD = ∼12 MV/cm from the direct current (DC) measurement. This suggests that the high E BD of h-BN can be the physical origin of the ultrafast operation.

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Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

Cited by 4 publications

References 45 publications

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Channel shape and interpoly dielectric material effects on electrical characteristics of floating-gate-type three-dimensional fin channel flash memories

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

Ultrafast Operation of 2D Heterostructured Nonvolatile Memory Devices Provided by the Strong Short-Time Dielectric Breakdown Strength ofh-BN

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