Experimental Validation of a High-Voltage Compliant Neural Stimulator implemented in a Standard 1.8V/3.3V CMOS Process

Abstract

This paper describes a neural stimulator with 4 × VDD compliance voltage, delivering up to 2.08 mA, and implemented in a standard 180 nm 1.8V/3.3V CMOS Process. The wide range of stimulation currents and high compliance voltage makes it suitable for stimulation applications both in rodents and mammals. Besides, it can be configured both as electrical and optical stimulator. Stacked transistor cells with dynamic gate biasing have been used for withstanding voltages well above the nominal supply. The system has been fabricated, occupying an active area of 2.34 mm 2 . The circuit has been experimentally tested by connecting it to a custom µelectrode array which was immersed into a phosphate-buffered saline solution.