Experimental vortex transitional nondestructive read-out Josephson memory cell

Tahara, S.; Ishida, I.; Ajisawa, Yumi; Wada, Yoshifusa

doi:10.1063/1.343077

Cited by 32 publications

(16 citation statements)

References 6 publications

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“…Unfortunately, it has not been complemented by a similar revolution in JJ-based random access memories (RAM). The development of superconductor RAMs slowed down after the demonstration of a Vortex Transitional (VT) memory cell [5], [6] and VT-based RAM circuits in 1990s [7], [8]. The 4-Kbit level of RAM integration achieved at that time was in line with available fabrication technologies.…”

Section: Introductionmentioning

confidence: 99%

“…The first [6] and the last [20] of the demonstrated VT cells occupied areas of 49 µm x 49 µm and 25 µm x 25 µm, respectively. The smallest VT cell was fabricated using e-beam lithography and had area of 9.5 µm x 12 µm [21].…”

Section: Introductionmentioning

confidence: 99%

“…Cumulative margins of 70 cells in the 12 x 6 array are shown. Cells(5,2) and(5,6) failed and were excluded from the test.…”

mentioning

confidence: 99%

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Семенов

Polyakov

Tolpygo

2019

IEEE Trans. Appl. Supercond.

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Arrays of Vortex Transitional (VT) memory cells with functional density up to 1 Mbit/cm 2 have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory.As a starting point, we developed a demo array of VT cells for the 100-μA/μm 2 MIT LL fabrication process SFQ5ee with 8 niobium layers. The studied two-junction memory cell with a twojunction nondestructive readout occupied 168 μm 2 , resulting in an over 0.5 Mbit/cm 2 functional density. Then, we reduced the cell area down to 99 μm 2 (corresponding to over 0.9 Mbit/cm 2 functional density) by utilizing self-shunted Josephson Junctions (JJs) with critical current density, Jc of 600 µA/μm 2 and eliminating shunt resistors. The fabricated high-Jc memory cells were fully operational and possessed wide Read/Write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: a) miniaturization of superconducting transformers by using soft magnetic materials; b) reduction of JJ area by using planar high-Jc junctions similar to variable thickness bridges.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Семенов

Polyakov

Tolpygo

2019

IEEE Trans. Appl. Supercond.

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“…Serial memories applicable to some instrumentation applications [22] did not go further either, as a 1 kbit memory occupied a substantial area [23] making it hardly extendible to application requirements. Superconducting memory exhibits relatively low density due to relatively large size of SQUID-based memory cells coupled to address lines via transformers which are difficult to scale [13]- [21]. Additionally, the RAM ac power was identified as an obstacle for the development of larger size memories [21].…”

Section: Introductionmentioning

confidence: 99%

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Vernik

Bolginov

Bakurskiy

et al. 2013

IEEE Trans. Appl. Supercond.

146

105

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We investigate a Magnetic Josephson Junction (MJJ) -a superconducting device with ferromagnetic barrier for a scalable high-density cryogenic memory compatible with energyefficient single flux quantum (SFQ) circuits. The superconductorinsulator-superconductor-ferromagnet-superconductor (SIS FS) MJJs are analyzed both experimentally and theoretically. We found that the properties of SIS FS junctions fall into two distinct classes based on the thickness of S layer. We fabricate Nb-Al/AlOx-Nb-PdFe-Nb SIS FS MJJs using a co-processing approach with a combination of HYPRES and ISSP fabrication processes. The resultant SIS FS structure with thin superconducting S -layer is substantially affected by the ferromagnetic layer as a whole. We fabricate these type of junctions to reach the device compatibility with conventional SIS junctions used for superconducting SFQ electronics to ensure a seamless integration of MJJ-based circuits and SIS JJ-based ultra-fast digital SFQ circuits. We report experimental results for MJJs, demonstrating their applicability for superconducting memory and digital circuits. These MJJs exhibit I c R n product only ∼30% lower than that of conventional SIS junctions co-produced in the same fabrication. Analytical calculations for these SIS FS structures are in a good agreement with the experiment. We discuss application of MJJ devices for memory and programmable logic circuits.Index Terms-Energy efficient, memory devices, proximity effect, RAM, single flux quantum, superconducting logic elements.

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“…SFQ logic works only at the 4K cryogenic temperature, so the SPM of a SFQbased CNN accelerator has to use cryogenic memory technologies that can maintain their functionality and reliability at 4K. SOTA [44,46], Josephson-CMOS SRAM [11,37,48], Magnetic Memory (MRAM) [38], and Superconducting Nanowire Memory (SNM) [3,61]. First, prior cryogenic memory technologies use SFQbased decoders, thereby suffering from large hardware overhead, due to the fan-out limitation of SFQ gates.…”

Section: Introductionmentioning

confidence: 99%

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators

Zokaee

Jiang

2021

MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture

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Ultra-fast & low-power superconductor single-flux-quantum (SFQ)based CNN systolic accelerators are built to enhance the CNN inference throughput. However, shift-register (SHIFT)-based scratchpad memory (SPM) arrays prevent a SFQ CNN accelerator from exceeding 40% of its peak throughput, due to the lack of random access capability. This paper first documents our study of a variety of cryogenic memory technologies, including Vortex Transition Memory (VTM), Josephson-CMOS SRAM, MRAM, and Superconducting Nanowire Memory, during which we found that none of the aforementioned technologies made a SFQ CNN accelerator achieve high throughput, small area, and low power simultaneously. Second, we present a heterogeneous SPM architecture, SMART, composed of SHIFT arrays and a random access array to improve the inference throughput of a SFQ CNN systolic accelerator. Third, we propose a fast, low-power and dense pipelined random access CMOS-SFQ array by building SFQ passive-transmission-line-based H-Trees that connect CMOS sub-banks. Finally, we create an ILP-based compiler to deploy CNN models on SMART. Experimental results show that, with the same chip area overhead, compared to the latest SHIFT-based SFQ CNN accelerator, SMART improves the inference throughput by 3.9× (2.2×), and reduces the inference energy by 86% (71%) when inferring a single image (a batch of images).

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Experimental vortex transitional nondestructive read-out Josephson memory cell

Cited by 32 publications

References 6 publications

Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Very Large Scale Integration of Josephson-Junction-Based Superconductor Random Access Memories

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators

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