Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach

Abstract

Fast reconfiguration is a mandatory feature for reconfigurable computing architectures. Research in this area has been increasingly focusing on new reconfiguration techniques that can sustain the architecture performance and to allow the simultaneous execution, at the same stage, of configuration and computation tasks. In this context, this paper presents a new dynamic reconfiguration technique, based on a configuration cache, that tackles this challenge by configuring and executing operations on functional units during the execution stage. This approach is implemented in a pipelined reconfigurable multiple-issue architecture called 2D-VLIW. Our dynamic reconfiguration technique takes advantage of the 2D-VLIW pipelined execution by starting reconfiguration concurrently to activities like reading operand registers and executing operations.

Function-Level Multitasking Interface Design in an Embedded Operating System with Reconfigurable Hardware

“…The instructionlevel processing engines are usually implemented as co-processors. For example, Santos, Azevedo, and Araujo presented an instruction-level reconfigurable architecture called the 2D-VLIW [7]. In the 2D-VLIW project, the processing engines are controlled by 2D-VLIW instructions which are composed of multiple single operations.…”

“…The category of the finest accelerating granularity consists of instruction-level processing engines, such as the 2D-VLIW approach [7]. The reconfigurable device operates as a co-processor to execute the task instructionby-instruction.…”

Pbiw

“…A arquitetura 2D-VLIW [36,37,38,39] é uma arquitetura de alto desempenho que utiliza uma codificação VLIW-Like composta por operações RISC e possui os estágios de:…”