Exploiting narrow-width values for improving non-volatile cache lifetime

Abstract

Abstract-Due to the high cell density, low leakage power consumption, and less vulnerability to soft errors, non-volatile memory technologies are among the most promising alternatives for replacing the traditional DRAM and SRAM technologies used in implementing main memory and caches in the modern microprocessor. However, one of the difficulties is the limited write endurance of most non-volatile memory technologies. In this paper, we propose to exploit the narrow-width values to improve the lifetime of non-volatile last level caches. Leading zeros masking scheme is first proposed to reduce the write stress to the upper half of the narrow-width data. To balance the write variations between the upper half and the lower half of the narrow-width data, two swap schemes, the swap on write (SW) and swap on replacement (SRepl), are proposed. To further reduce the write stress to non-volatile caches, we adopt two optimization schemes, the multiple dirty bit (MDB) and read before write (RBW), to improve their lifetime. Our experimental results show that by combining all our proposed schemes, the lifetime of non-volatile caches can be improved by 245% on average.

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

“…These small values are called narrow-width values. This wellknown characteristic of the applications has been utilized frequently in many prior works for power, performance, and fault-tolerance optimizations [16], [18], [19], [32], [33]. In a narrow-width value, high-order bits (i.e., most significant bits) are all zeros.…”

“…Many prior works have shown similar observations. In [33], it is pointed out that more than 40% of the data is the narrow-width value. In [19], it is also pointed out that around 50% of the instructions use the narrow-width values as their operands.…”

Exploiting bit-level write patterns to reduce energy consumption in hybrid cache architecture

“…It is known that the majority of data require fewer bits out of all of the bits in the cache line [24]. The authors of previous papers have enhanced the utility of SRAM in HCAs by exploiting narrow-width values [25] [26]. Even though they are different as an aspect of ways to deal with the NVM region, they laid the common foundation of cache line granularity.…”

Exploiting Non‐Leading Zeroes to Reduce Energy Consumption for Non‐Volatile Memories

“…However, STT-RAM also has comparable penalty for write operations in terms of dynamic energy consumption and write latency. Several schemes have been explored to avoid unnecessary write operations to address write-related drawbacks [2][3][4].…”

“…In addition to the RBW, some researchers introduced the narrow-width values (NWV) scheme [3,4]. The main idea comes from the fact that a small value requires fewer bits to represent the data.…”