Exploiting parallelism to speed up circuit legalization

Netto, Renan; Guth, Chrystian; Livramento, Vinicius; Castro, Márcio; Pilla, Laércio Lima; Güntzel, José Luís

doi:10.1109/icecs.2016.7841279

Cited by 3 publications

(3 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [71], standard cells are legalized, relying on fast queries on multidimensional trees. In [72], a legalization algorithm that explores parallelism to reduce legalization runtime is shown. In [73], a multi-deck legalization technique is presented.…”

Section: Legalizationmentioning

confidence: 99%

VLSI Placement Optimization Algorithms

Monteiro

2022

JICS

View full text Add to dashboard Cite

Placement is a fundamental optimization step to compute cell locations. The quality of results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement solution. The placement optimization flow is split into (1)global placement, (2) legalization, and (3) detailed placement. In global placement, cell locations are computed to minimize total wire length subject to a maximum cell density threshold. The cell overlapping and cell alignment to site row boundaries are relaxed. In legalization, cells are placed in locations free of overlapping and aligned to site row boundaries. Legalization algorithms compute cell locations with minimized cell displacement. In detailed placement, objectives are optimized locally. Detailed placement algorithms iterate over one cell or a small set of cells. The traditional optimization objective is total wire length. Placement algorithms also address timing violations, routability, design rules, and so forth. The placement algorithms rely on heuristics and formal methods to compute optimized cell locations. Moreover, placement algorithms require models to address signal delay propagation, area density, routing congestion, hyper-edge nets, and so forth. In the literature, several algorithms have been presented to improve placement solutions. On the other hand, placement is a really challenging problem that continues to have space for further improvement and for innovative algorithms.

show abstract

Section: Legalizationmentioning

confidence: 99%

VLSI Placement Optimization Algorithms

Monteiro

2022

JICS

View full text Add to dashboard Cite

show abstract

“…Abacus is used in the density-aware detailed placement flow in the literature [11] in order to legalize the placement instances produced after each cell swap is performed by the detailed placer. In the literature [12], a parallel version of the Abacus algorithm is implemented and evaluated. Parallelization was achieved by spawning multiple threads in order to evaluate candidate row positions.…”

Section: Related Workmentioning

confidence: 99%

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

et al. 2018

View full text Add to dashboard Cite

In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

show abstract

“…The solutions presented in this thesis bring innovations that were recognized by the scientific community, leading to 3 article publications [Livramento et al 2014] and 5 conference papers [Guth et al 2015, Netto et al 2016c, Netto et al 2016a]. Besides, the implementation of the proposed technique for Problem 1 was submitted to the international contest on Computer-Aided Design to allow a direct comparison of their results with other groups worldwide.…”

Section: Introduction Identification Of the Target Problems And Publicationsmentioning

confidence: 99%

Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

Livramento¹,

Güntzel²

2017

Anais Do XXX Concurso De Teses E Dissertações (CTD 2017)

View full text Add to dashboard Cite

The evolution of CMOS technology made possible integrated circuits with billions of transistors assembled into a single silicon chip, giving rise to the jargon Very-Large-Scale Integration (VLSI). VLSI circuits span a wide range class of applications, including Application Specific Circuits and Systems-On-Chip. The latter are responsible for fueling the consumer electronics market, especially in the segment of smartphones and tablets, which are responsible for pushing hardware performance requirements every new generation. The required clock frequency affects the performance of a VLSI circuit and induces timing constraints that must be properly handled by synthesis tools. This thesis focuses on techniques for timing closure of cellbased VLSI circuits, i.e. techniques able to iteratively reduce the number of timing violations until the synthesis of the synchronous digital system reaches the specified target frequency.

show abstract

Exploiting parallelism to speed up circuit legalization

Cited by 3 publications

References 14 publications

VLSI Placement Optimization Algorithms

VLSI Placement Optimization Algorithms

Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Timing Optimization During the Physical Synthesis of Cell-Based VLSI Circuits

Contact Info

Product

Resources

About