Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing

Abstract

Runtime Reconfiguration (RTR) has been traditionally utilized as a means for exploiting the flexibility of High-Performance Reconfigurable Computers (HPRCs). However, the RTR feature comes with the cost of high configuration overhead which might negatively impact the overall performance. Currently, modern FPGAs have more advanced mechanisms for reducing the configuration overheads, particularly Partial Runtime Reconfiguration (PRTR). It has been perceived that PRTR on HPRC systems can be the trend for improving the performance. In this work, we will investigate the potential of PRTR on HPRC by formally analyzing the execution model and experimentally verifying our analytical findings by enabling PRTR for the first time, to the best of our knowledge, on one of the current HPRC systems, Cray XD1. Our approach is general and can be applied to any of the available HPRC systems. The paper will conclude with recommendations and conditions, based on our conceptual and experimental work, for the optimal utilization of PRTR as well as possible future usage in HPRC.

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

“…To analyse the effect of different PR schemes on overall system performance, we consider a case study from [4]. The experiment involves image edge detection after a low-pass filter is applied.…”

The Paramountcy of Reconfigurable Computing

“…FPGAs are supposed to be in 70% of all Embedded systems 228 . Introduced in 1984, fastest-growing segment of the semiconductor industry for about two decades, now a 4 billion US-$ world market (almost 30% increase from last year -Peter Clarke from iSuppli estimates 43%) FPGAs are a well proven technology rapidly heading for mainstream and also used in supercomputing by Cray, Silicon Graphics, and others 98,[241][242][243] . Estimations of the number of designers actively involved in FPGA design range from about 100,000 to over 500,000 engineers worldwide.…”

“…Apart from ERC (Embedded Reconfigurable Computing) we have another reconfigurable computing scene: HPRC (High Performance Reconfigurable Computing [241][242][243] ). This is the combination of supercomputing and the use of reconfigurable platforms.…”

“…This is scene leading us toward the dominance of heterogeneous systems. A problem yet to be solved here is programmer productivity [241][242][243] . Programmers cannot work with hardware description languages like FPGA experts 147 .…”

Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems

“…RELATED WORK Four interesting recent articles [12], [13], [14], [15] have analyzed the impact of loading the configurations at run-time from a non-volatile external memory. The experimental results presented in [12] conclude that the reconfiguration speed is three orders of magnitude worse than the peak reconfiguration speed of the device if a flash memory is used to store the configurations.…”