Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs

Shim, Youngseop; Kim, Myungsuk; Chun, Myoungjun; Park, Jisung; Kim, Yoona; Kim, Jihong

doi:10.1145/3352460.3358311

Cited by 33 publications

(32 citation statements)

References 9 publications

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“…If a cell's V TH level moves beyond the V REF value, a bit error occurs as the cell's data is sensed to be different from the data originally programmed into it. Prior works show that retention loss is the dominant source of errors in 3D NAND flash memory [7,49,65,66,84]. Compared to 2x-nm planar NAND flash memory, 3D NAND flash memory experiences 40% less program interference and 96.7% weaker read disturbance while it suffers from a larger number of retention errors that occur faster [66].…”

Section: Reliability Problems In Nand Flashmentioning

confidence: 99%

“…Prior works propose several techniques that reduce the number of retry steps [12, 13, 64-66, 77, 84], but read-retry is difficult to completely avoid in modern SSDs as V OPT quickly and significantly changes over time. For example, an existing technique can reduce the average number of read-retry steps by about 70% under a 1-year retention age at 2K P/E cycles, but for every page read, it requires at least three retry steps [84].…”

Section: Read-retry In Modern Nand Flashmentioning

confidence: 99%

“…A read-retry operation repeats a retry step until it finds V REF values that allow the page's raw bit-error rate (RBER) to be lower than the ECC correction capability (i.e., the number of errors correctable) or finds for sure that the page cannot be read without errors. Recent work [84] shows that a modern SSD with long retention age values (i.e., how long data is stored after it is programmed) and high program/erase (P/E) cycles (i.e., how 1 A NAND flash memory concurrently reads and writes multiple cells at a page (e.g., 16 KiB) granularity (see Section 2.2). many writes/erases are performed) suffers from a large number of read-retry operations that increase the read latency linearly with the number of retry steps.…”

Section: Introductionmentioning

confidence: 99%

“…Prior works [12, 13, 64-66, 77, 84] attempt to reduce the number of retry steps by quickly identifying near-optimal V REF values, but read-retry is a fundamental problem that is difficult to completely eliminate in modern SSDs. For example, an existing technique [84] reads a page using V REF values that have been recently used for a read-retry operation on other pages exhibiting similar error characteristics with the page to read. Doing so significantly reduces the number of retry steps by starting a read (and retry) operation with the V REF values close to the optimal read-reference voltage (V OPT ) values.…”

Section: Introductionmentioning

confidence: 99%

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Reducing solid-state drive read latency by optimizing read-retry

Park

Kim

Chun

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly increase the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR 2 ) and 2) Adaptive Read-Retry (AR 2 ). PR 2 reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR 2 shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average) over a state-of-the-art baseline with only small changes to the SSD controller. CCS CONCEPTS• Hardware → External storage.

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Section: Reliability Problems In Nand Flashmentioning

confidence: 99%

Section: Read-retry In Modern Nand Flashmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reducing solid-state drive read latency by optimizing read-retry

Park

Kim

Chun

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

Self Cite

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“…We refer to the number of read-retry operation as RL (Read-Level) below. Many research works have devoted to the optimization of large read latency in the aged SSD [11,12,13]. As the NAND flash adjusts the read voltage to sense the electrons in the cell incrementally, these methods proposed to keep track of the last successful RL for the future reads at different granularity(i.e., page-level, block-level, and layer-level).…”

Section: Introductionmentioning

confidence: 99%

Error source and latency-aware read performance optimization scheme for aged SSDs

Nie

Zhang

et al. 2021

IEICE Electron. Express

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LDPC code has been used widely in NAND flash-based storage system due to its high error correction capacity, prolonging the lifetime of multi-bit NAND flash. However, the LDPC decoding latency degrades the read performance of SSD as it induces more read-retry operations. The last RL(Read-Level) recording method has been proposed in recent research works, which achieves better performance improvement by reducing many useless fail reads. However, these schemes reset the RL of these pages to be 1 after these blocks are erased. Using RL 1 to read these pages may induce many fail reads at first read on each page. That because it ignores the different error source issues, i.e., a part of the page error comes from the P/E cycles, while others come from retention time and other sources. Motivated by this observation, in this paper, we propose two schemes to optimize the read procedure of NAND flash-based SSD, especially for aged SSDs. We propose to record RL induced by different error sources separately, so the RL of the page could keep unchanged rather than 1 after the blocks are erased. The scheme could reduces useless fail read after the blocks are read at first time. We also design a latency aware I/O scheduler to reorder the input read requests in batch by prioritizing requests with low latency to reduce the queue latency. Our experiments show that the proposed scheme can reduce the average response time by up to 33% with less storage overhead.

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Stop unnecessary refreshing: extending 3D NAND flash lifetime with ORBER

Gao

et al. 2022

CCF Trans. HPC

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Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs

Cited by 33 publications

References 9 publications

Reducing solid-state drive read latency by optimizing read-retry

Reducing solid-state drive read latency by optimizing read-retry

Error source and latency-aware read performance optimization scheme for aged SSDs

Stop unnecessary refreshing: extending 3D NAND flash lifetime with ORBER

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