Exploiting recent SIMD architectural advances for irregular applications

Abstract

A broad class of applications involve indirect or datadependent memory accesses and are referred to as irregular applications. Recent developments in SIMD architectures-specifically, the emergence of wider SIMD lanes, combination of SIMD parallelism with many-core MIMD parallelism, and more flexible programming APIs-are providing new opportunities as well as challenges for this class of applications. In this paper, we propose a general optimization methodology, to effectively optimize different subclasses of irregular applications. Based on the observation that all applications with indirect memory accesses can be viewed as sparse matrix computations, we design an optimization methodology, which includes three sub-steps: 1) locality enhancement through tiling, 2) data access pattern identification, and 3) write conflict removal at both SIMD and MIMD levels. This method has been applied to unstructured grids, molecular dynamics, and graph applications, in addition to sparse matrix computations. The speedups achieved by our single threaded vectorized code over serial code is up to 9.05, whereas the overall speedup while utilizing both SIMD and MIMD (61 cores in Intel Xeon Phi) with our approach is up to 467.1. Further optimization using matrix reordering on irregular reductions and graph algorithms is able to achieve an incremental speedup of up to 1.69, though at a relatively high preprocessing cost. Moreover, SpMM using our approach outperforms routines from a highly optimized commercial library by up to 2.81x.

Graphphi

“…For stripe splitting mode, we need to run a lock-based code for tiles in the same stripe as we mentioned before. In SIMD-level, as opposed to previous efforts based on a heavy data reorganization preprocessing [11], we rely on the built-in conflicts detection intrinsics provided by Xeon Phi to dynamically address the possible update conflicts.…”

“…GraphPhi focuses on a different throughputoriented architecture and explores many unique features that are not shown on GPUs. There are also some optimization techniques for Xeon Phi [6,11,22]. Although they comprehensively explore advanced SIMD execution, none of them offer a general graph processing framework by effectively exploiting both MIMD and SIMD execution, or emerging HBM techniques.…”

“…There exist several graph processing frameworks and libraries based on popular many-core processors such as GPUs [23,44] and early versions of Xeon Phis [11,22,29]. In addition, many other graph processing frameworks [33,40] designed for shared-memory multi-core CPUs are also capable of running on Xeon Phis owing to their x86-compatibility.…”

Efficient and high‐quality sparse graph coloring on GPUs

“…Green‐Marl is a domain specific language for graph processing. Chen et al proposed compiler optimization methodology for graph and other irregular applications on Intel Xeon Phi coprocessors. Ahn et al developed a customized processing‐in‐memory (PIM) accelerator for large‐scale graph processing.…”

Potential benefits of a block-space GPU approach for discrete tetrahedral domains

“…al. propose a general optimization technique for data-parallel problems with indirect memory accesses [1], by viewing the problem as a sparse matrix computation. Yavors'kii and Weigel identified that tiled computations, such as the ones found in spin systems, are greatly improved by re-organizing the memory in blocks [12].…”