Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology

Nguyen, Huy H.; John, Lizy K.

doi:10.1145/305138.305150

Cited by 64 publications

(27 citation statements)

References 3 publications

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“…With recent releases of G4 PowerPC processors with AltiVec and the AltiVec enabled C compiler, we can confirm the evaluations assessed with various simulators [7].…”

Section: Proposed Implementationsupporting

confidence: 64%

Optimization of vertical and horizontal beamforming kernels on the PowerPC G4 processor with AltiVec technology

Cho

Brunke²,

Allen³

et al.

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)

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Real-time digital sonar beamforming is a computationally intensive algorithm that has been implemented in the past primarily in custom embedded hardware. With recent advancements in native signal processing extensions for general-purpose processors, it is possible to implement sonar beamforming using off-the-shelf hardware. Current implementation on a Sun UltraSPARC multiprocessor suggests a very promising platform for transitioning such applications to general-purpose systems. This paper proposes to

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“…With recent releases of G4 PowerPC processors with AltiVec and the AltiVec enabled C compiler, we can confirm the evaluations assessed with various simulators [7].…”

Section: Proposed Implementationsupporting

confidence: 64%

Optimization of vertical and horizontal beamforming kernels on the PowerPC G4 processor with AltiVec technology

Cho

Brunke²,

Allen³

et al.

Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)

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show abstract

“…Matrix multiplication is a common function used in DSP and multimedia applications [15]. To illustrate how attributes such as SoO and interconnection affect algorithm mapping, matrix multiplication of two 4x4 matrices was mapped to the CGRA-A, CGRA-B and CGRA-C architectures.…”

Section: Application Mappingmentioning

confidence: 99%

Rapid functional modelling and simulation of coarse grained reconfigurable array architectures

Patel

McGettrick

Bleakley

2011

Journal of Systems Architecture

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Publication informationJournal of Systems Architecture, 57 (4): 383-391Publisher Elsevier Item record/more information http://hdl.handle.net/10197/7037 Publisher's statementThis is the author's version of a work that was accepted for publication in Journal of Systems Architecture. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Journal of Systems Architecture (VOL 57, ISSUE 4, (2011) Due to the large number of design options available, it is difficult for designers to make optimal design decisions in the early stages of the design cycle. This paper proposes a novel functional modelling framework for CGRA architectures which makes the design space exploration process easier and faster. The framework allows architecture modelling, application mapping and simulation in a single environment, avoiding development of a complex tool set. The proposed approach provides flexibility which allows users to quickly investigate many design options without remodelling. The usefulness and extensibility of the framework is illustrated by presentation of a case study and associated design metrics.

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“…Harnessing data parallelism using short vector or SIMD architectures is a popular approach [20,1]. This technique has been shown to improve performance by up to an order of magnitude on DSP style algorithms and even on some small speech processing codes [13].…”

Section: Related Workmentioning

confidence: 99%

A low power architecture for embedded perception

Mathew

Davis

Parker

2004

Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of complex perception applications cannot be met by current embedded processors and often even exceed the performance of high performance microprocessors whose energy consumption far exceeds embedded energy budgets. Though custom ASICs provide a solution to this problem, they incur expensive and lengthy design cycles and are inflexible. This paper introduces a VLIW perception processor which uses a combination of clustered function units, compiler controlled dataflow and compiler controlled clock-gating in conjunction with a scratch-pad memory system to achieve high performance for perceptual algorithms at low energy consumption. The architecture is evaluated using ten benchmark applications taken from complex speech and visual feature recognition, security, and signal processing domains. The energydelay product of a 0.13µ implementation of this architecture is compared against ASICs and general purpose processors. Using a combination of Spice simulations and real processor power measurements, we show that the cluster running at 1 GHz clock frequency outperforms a 2.4 GHz Pentium 4 by a factor of 1.75 while simultaneously achieving 159 times better energy delay product than a low power Intel XScale embedded processor.

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Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology

Cited by 64 publications

References 3 publications

Optimization of vertical and horizontal beamforming kernels on the PowerPC G4 processor with AltiVec technology

Optimization of vertical and horizontal beamforming kernels on the PowerPC G4 processor with AltiVec technology

Rapid functional modelling and simulation of coarse grained reconfigurable array architectures

A low power architecture for embedded perception

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