Exploiting TLM and Object Introspection for System-Level Simulation

Beltrame, Giovanni; Sciuto, D.; Silvano, Cristina; Lyonnard, D.; Pilkington, Chuck

doi:10.1109/date.2006.244004

Cited by 16 publications

(14 citation statements)

References 7 publications

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“…Designers can use an appropriate abstraction to describe the system behavior of an architecture under development; perform simulations to validate the functionality of the architecture, and track system performance [7]- [9]. Few works have developed approaches that facilitate rapid design space exploration by improving the speed of each simulation run [12]- [14]. The accuracy and speed of a simulation-based approach depend on the abstraction of the model.…”

Section: Related Workmentioning

confidence: 99%

A fast and effective dynamic trace-based method for analyzing architectural performance

Chen¹,

Chiou²,

Chang³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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Performance estimation at system-level involves quantitative analysis to allow designers to evaluate alternative architectures before implementation. However, designers must spend a tremendous amount of time in system remodeling for performance estimation for each alternative solution in a huge design space. The effort required for system remodeling prolongs the exploration step. Furthermore, the accuracy and speed of performance analysis affects the effectiveness of architectural exploration. This work presents an architectural performance analysis using a dynamic trace-based method (APDT) to reduce the effort required for system remodeling and the time required to estimate performance during architecture exploration, thereby improving the effectiveness of that exploration. Experimental results demonstrate that the APDT approach is faster than the bus functional-level simulation on CoWare with a minor average deviation.

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Section: Related Workmentioning

confidence: 99%

A fast and effective dynamic trace-based method for analyzing architectural performance

Chen¹,

Chiou²,

Chang³

2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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“…In [24] the authors switch between abstraction levels in order to obtain either accuracy or simulation speed. The most accurate abstraction level allows to debug and optimize the system on specific execution phases, otherwise a more abstract level is used to speedup the system simulation.…”

Section: Related Workmentioning

confidence: 99%

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

Massas

Pétrot

2010

Des Autom Embed Syst

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International audienceThis paper presents a novel simulation-based approach which targets the performance estimation of cache coherence protocol implementations. Our approach allows to model a cache coherence protocol where coherence transactions take zero cycle and do not generate communication accesses, in the hope that it will provide a close lower bound on latency and traffic. The protocol modeling approach relies on cycle-accurate simulation models in which components can access instantaneously and transparently internal states of other components. Using this strategy, the access time and the traffic due to cache misses are taken into account as it would be on a multiprocessor system without cache coherence. However, the proposed approach still ensures that processors receive coherent data. We detail the implementation of this approach in a cycle accurate multiprocessor simulation environment. To show its effectiveness, we implement cache and memory models for two coherence protocols both with and without our omniscient cache coherence (OCC) proposal. We show with a formal method that this approach makes it possible to preserve the consistency models implied by the cache coherence protocols, and experimentally that the OCC strategy protocol gives a close lower bound on latency and traffic

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“…Schriner et al report a quantitative analysis of speed-accuracy tradeoff of TLM, using the advanced high-performance bus (AHB) as a test case, at different abstraction levels [25]. Beltrame et al proposed using multiple levels of abstraction for communication architecture exploration, with the ability to dynamically shift between BCA, untimed TLM and timed TLM abstractions to improve simulation speed [26]. A simulation-based method gives accurate estimation results but pays too heavy a computational cost with increasing number of bus requests and simulation iterations.…”

Section: Related Workmentioning

confidence: 99%

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

Shafiq

Isshiki

2017

IPSJ Transactions on System LSI Design Methodology

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Accurate and fast performance estimation methods for modern and future multi-core systems are the focal point of much research due to the complexity associated with such architectures. The communication architecture of such systems has a huge impact on the performance and power of the whole system. Architects need to explore many design possibilities by using performance estimation techniques at early stages of design to make design decisions earlier in the design cycle. While software developers need to develop and test applications for the target architecture and gather performance measurements as early in the design cycle as possible. Full system simulation techniques provide accurate performance values but are extremely time consuming. Static analysis techniques are fast but cannot capture the dynamic behavior associated with shared resource contention and arbitration. Moreover, synthetic traffic patterns have been used to analyze the communication architecture however, such patterns are not realistic enough. We propose a statistical based model to predict the dynamic cost of bus arbitration on the performance of a bus architecture. The proposed model uses workload trace of the actual applications and benchmarks to capture the real application traffic behavior. Statistics on the traffic patterns are collected and input to the analytical model which calculates performance values for the communication architecture under consideration. By knowing the performance measures, designers can avoid over and under-design of the communication architecture. This paper builds up on a previously developed performance estimation model. The previous work modeled single and burst bus-transfers, however only one interfering bus master at a time for each blocked bus request was considered. The proposed, improved accuracy model considers multiple interfering masters for each blocked request hence improving the estimation accuracy especially for traffic intensive applications and many PE architectures. Experiments are performed for two different architectures i.e., 4 processing elements connected via a shared bus and 8 processing elements connected via a shared bus. Results show no significant difference in accuracy compared to previously developed model, for low traffic applications SPARSE and ROBOT however notable accuracy improvement for traffic intensive applications. Maximum estimation error is reduced from 1.75% to 0.6% for FPPPP and from maximum 13.91% to 8.8% for FFT on the 4PE architecture. On the 8PE architecture, maximum estimation error is reduced from 11.8% to 2.7% for the FPPP benchmark. Moreover simulation speed-up for the proposed technique over simulation method is reported.

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Exploiting TLM and Object Introspection for System-Level Simulation

Cited by 16 publications

References 7 publications

A fast and effective dynamic trace-based method for analyzing architectural performance

A fast and effective dynamic trace-based method for analyzing architectural performance

Evaluation of the implementation cost of cache coherence protocols using omniscient actions

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

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