Exploiting transistor-level reconfiguration to optimize combinational circuits

Raitza, Michael; Kumar, Akash; Völp, Marcus; Walter, Dennis; Trommer, Jens; Mikolajick, Thomas; Weber, Walter M.

doi:10.23919/date.2017.7927013

Cited by 50 publications

(26 citation statements)

References 14 publications

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“…Note, that in this early TRL stage, questions regarding physical layout and area cannot be answered seriously, yet. Though, estimations from [20]- [22] indicate that, depending on the individual benchmark circuit, reconfigurable transistor area requirements range from being competitive (17 % overhead) to even surpassing (41 % benefit) CMOS designs. For more insights into the physics and constraints of the reconfigurable technology, the reader is referred to the cited literature.…”

Section: Related Workmentioning

confidence: 99%

“…The branches connected to inputs and are implemented as static N-/P-branches. The second from the left variant (2i) is the fully reconfigurable circuit from [20], which is reconfigurable in input only. Up to now, all circuits are of the i type, optimizing the non-reconfiguration inputs and .…”

Section: -Min Circuit -8 Topologies With 2 Types Eachmentioning

confidence: 99%

“…Up to now, all circuits are of the i type, optimizing the non-reconfiguration inputs and . The innermost circuit variant (2s) is also known from [20] and differs from (2i) only by using the source-side SB gate to connect inputs, too. Leftmost of to its simple structure, saving transistor gates outperforms (in terms of delay) its i type counterpart.…”

Section: -Min Circuit -8 Topologies With 2 Types Eachmentioning

confidence: 99%

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Quantitative Characterization of Reconfigurable Transistor Logic Gates

et al. 2020

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We present a new approach for early analysis of logic gates that is based on formal methods. As device technology research takes years and is very expensive, it is desirable to evaluate a technology's potential as early as possible, which is hard to do with current techniques. The actual impact of new devices on circuit design and their performance in complex circuits, are difficult to predict using simulationbased techniques. We propose a new approach that supplements simulation-based analysis and enables the development of standard cells alongside ongoing fundamental device research. Thereby, it potentially shortens the development cycle and time to market of a new technology. We develop a new discrete charge-transport model for electrical networks and a new flexible model of polarity-reconfigurable transistors as our formal basis. These models make circuit designs accessible to an analysis using probabilistic model checking and power our experiments. Besides worst-case analysis, we leverage measures hardly accessible to simulation such as average delay and average energy consumption per switching operation. We complement this with an automated design-space exploration that yields all reasonable implementations of a switching function built with reconfigurable transistors. After demonstrating the accuracy of our approach by comparison with finite element method analysis results, we undergo a comprehensive design-space exploration and analysis of the 3-minority function. The quantitative results are ranked with respect to various performance metrics, and we analyze the most promising circuit implementations in detail to derive a design guide that yields the best implementation for given statistics of the input patterns.

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Section: Related Workmentioning

confidence: 99%

Section: -Min Circuit -8 Topologies With 2 Types Eachmentioning

confidence: 99%

Section: -Min Circuit -8 Topologies With 2 Types Eachmentioning

confidence: 99%

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Quantitative Characterization of Reconfigurable Transistor Logic Gates

et al. 2020

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“…. $15.00 https://doi.org/10.1145/3240765.3243472 delay (smaller critical paths [43]), area [56], and overall energydelay-product [48] for the entire circuit.…”

Section: Introductionmentioning

confidence: 99%

“…Apart from processing elements like adders which have been shown to exploit features of these re-configurable devices [43,2], memories also form a critical component. The emergence of new devices and technology enables blurring the gap between memory and logic functionality.…”

Section: Introductionmentioning

confidence: 99%

Emerging reconfigurable nanotechnologies

Rail

Srinivasa

Cadareanu

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

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Several emerging reconfigurable technologies have been explored in recent years offering device level runtime reconfigurability. These technologies offer the freedom to choose between p-and n-type functionality from a single transistor. In order to optimally utilize the feature-sets of these technologies, circuit designs and storage elements require novel design to complement the existing and future electronic requirements. An important aspect to sustain such endeavors is to supplement the existing design flow from the device level to the circuit level. This should be backed by a thorough evaluation so as to ascertain the feasibility of such explorations. Additionally, since these technologies offer runtime reconfigurability and often encapsulate more than one functions, hardware security features like polymorphic logic gates and on-chip key storage come naturally cheap with circuits based on these reconfigurable technologies. This paper presents innovative approaches devised for circuit designs harnessing the reconfigurable features of these nanotechnologies. New circuit design paradigms based on these nano devices will be discussed to brainstorm on exciting avenues for novel computing elements.

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Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

Fuchsberger

Wind

Sistani

et al. 2023

Adv Elect Materials

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Reconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si0.67Ge0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO2/HfO2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements.

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Exploiting transistor-level reconfiguration to optimize combinational circuits

Cited by 50 publications

References 14 publications

Quantitative Characterization of Reconfigurable Transistor Logic Gates

Quantitative Characterization of Reconfigurable Transistor Logic Gates

Emerging reconfigurable nanotechnologies

Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

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