Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance

Nanda, Swagat; Dhar, Rudra Sankar

doi:10.1016/j.compeleceng.2022.107687

Cited by 7 publications

(20 citation statements)

References 9 publications

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“…The 08 nm gate length TG QW-FinFET device is initially fabricated abreast a combined Si and buried oxide (BOX) layer height of ∼80 nm based on the device established by Nanda et al [23], for 10 nm channel length. Different nano devices are developed where the substrate and BOX heights are gradually decreased to study the effect of the BOX on various electrical parameters of the device.…”

Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

“…Finally, the QW-FinFET named Device D 3 is settled with s-Si 0.6 Ge 0.4 dimensions increased to 4 nm while the s-Si region is fixated at 1.5 nm. Devices D 4 and D 5 are the existing literature FinFET devices of 10 nm gate length of Nanda et al [23], and Bha et al [22], respectively, which are employed here for the validation and calibration of the novel QW-FinFETs developed and investigated here. Devices D 6 to D 10 are developed with similar structure of Device D 1 but with a combined height of substrate and BOX varying from 80 nm down to 40 nm with decrement of 10 nm.…”

Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

“…But the device has a lower on current requiring the need to search for devices with higher performance. Nanda et al designed a QWB n-FinFET collating the quantum effect and strained silicon engineering with a 10 nm gate length [23]. Due to the presence of three gates, the device conveyed an of 44% increase in the on current in comparison with the 10 nm SOI FinFET designed by Bha et al [22].…”

Section: Introductionmentioning

confidence: 99%

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Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ~25% enhancement in drain currents with Device D2 portraying almost ~103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.

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Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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“…The basic device structure is based on the 10 nm HOI FinFET developed by Nanda et al [20] considering a combined substrate and buried oxide height of 80 nm. The width and height of the initial device is kept at 6 nm considering the advantages of a square device depicted by Saha et al [21], and is designated device D 0 .…”

Section: Device Structure and Theorymentioning

confidence: 99%

“…The 1 nm underlap device gracefully achieved ∼25.3% reduction in DIBL in comparison to the 14 nm strained channel DGFET without underlap, nonetheless widening the research gap in terms of search for devices accommodating higher ON currents as per International Roadmap for Devices and Systems (IRDS 2018) [19]. Subsequently, Nanda et al [20] developed a 3D FinFET at 10 nm gate length with strained induced Heterostructure-On-Insulator channel Quantum Well Based (QWB) system comprising of three layers creating the hetero layered architecture (s-Si/ s-SiGe/s-Si) which had an ON current of 183.13 μA μm −1 and an off current of 0.384 nA μm −1 , which is contemplated as the fundamental structure for this paper.…”

Section: Introductionmentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.

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Analysis of breather-soliton, breather-breather and soliton-breather pair creation in saturating nonlinear media

Sarkar,

Dutta

2023

J Opt

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Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance

Cited by 7 publications

References 9 publications

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Analysis of breather-soliton, breather-breather and soliton-breather pair creation in saturating nonlinear media

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