Exploration of complex metal 2D design rules using inverse lithography

Abstract

As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k 1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as "hotspots." This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation.Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution.We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Comprehensive die-level assessment of design rules and layouts

“…NN testing on MIPS design ( a blind test case) and on FPU (used in training). This network has been trained resulting in a training mean square error of 8.16x10 4 libraries. However, this is impractically slow to explore design rule choices.…”

“…Unfortunately, even after decades of existence, DR evaluation is largely unsystematic and empirical in nature; it relies on limited and small-scale experiments and manufacturing tests and much on speculations based on technologists/designers experience with previous technology generations [1]- [4]. The work in [5] presents a flow for the optimization of double-patterning design rules.…”

“…The method consists of an optimization loop in which rules are modified, standard-cell layouts are generated, and printability is analyzed. Although this approach, like [3,4], may be suited for exploring rules from a pure printability perspective, it does not examine the electrical effects of rules. Moreover, because actual layout generation and printability analysis are excessively time-consuming, exploring a wide range of rules and rule combinations is impractical with these approaches.…”

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

“…For example, the work in [16] electrically evaluates line-end extension rule and conclude that it may be too conservative. Other recent works [17,18] offer solutions to explore DRs from a pure printability perspective and do not examine the effects of DRs on circuit characteristics. Moreover, none of these methods account for layout topology changes that may happen when the DR values change significantly.…”

A framework for early and systematic evaluation of design rules

“…For example, [16] evaluates line-end extension rule electrically to conclude that it may be too conservative. Other recent works [17,18] offer solutions to explore DRs from a pure printability perspective and do not examine the effects of DRs on circuit characteristics. Moreover, none of these methods account for layout topology changes that may happen when DR values change significantly.…”