Exploration of hardware sharing for image encoders

Abstract

Hardware sharing can be used to reduce the area and the power dissipation of a design. This is of particular interest in the field of image and video compression, where an encoder must deal with different design tradeoffs depending on the characteristics of the signal to be encoded and the constraints imposed by the users. This paper introduces a novel methodology for exploring the design space based on the amount of hardware sharing between different functional blocks, giving as a result a set of feasible solutions which are broad in terms of hardware cost and throughput capabilities. The proposed approach, inspired by the notion of a partition in set theory, has been applied to optimize and to evaluate the sharing alternatives of a group of image and video compression key computational kernels when mapped onto a Xilinx Virtex-5 FPGA.

Hardware resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures

“…At the opposite, in the second mode, the accelerator is placed outside the processor on a dedicated bus [8,10,11]. A group of closely coupled hardware components operates at a single clock cycle fixed by the slower components.…”

“…The integration of custom instruction in FPGA-based MPSoC increases the performance gain by incorporating hardware components to handle computational tasks [6][7][8][9]. Modern platforms, including FPGAs and ASICs support different couplings of hardware components with the processor.…”

Sensor Systems Based on FPGAs and Their Applications: A Survey

“…Kimura et al argued that the main problem of implementing compression algorithms on sensor nodes was the complexity and required time of execution [ 21 ]. Hence, FPGAs can be employed in this respect, for instance, to accelerate arithmetic applications via fast multipliers and adders [ 52 ].…”