Exploration of Loop Unroll Factors in High Level Synthesis

Panda, Preeti Ranjan; Sharma, Nalin Kumar; Kurra, Srikanth; Bhartia, Khushboo Anil; Singh, Neeraj Kumar

doi:10.1109/vlsid.2018.115

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…Kawamura et al 11 performed loop optimization techniques including loop flattening and trip count reduction to produce a more efficient Fast Number Theoretic Transform processor in HLS to be implemented on FPGA. Loop flattening is one of the loop optimization techniques apart from loop unrolling, 16 loop fusion, 17 and loop replication to name a few. Besides considering algorithm structure, 18 highlighted that the dependencies including loop dependencies and memory dependencies are worth considering in order to achieve more optimized pipelined hardware in HLS.…”

Section: Previous Workmentioning

confidence: 99%

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

Tan

Ooi

Choo

et al. 2021

Circuit Theory & Apps

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This paper describes a fast and efficient hardware-accelerated pseudoinverse computation through algorithm restructuring and leveraging FPGA synthesis directives for parallelism prior to high-level synthesis (HLS). The algorithm, which is composed of modified Gram-Schmidt QR decomposition (MGS-QRD), triangular matrix inversion (TMI), and matrix multiplication (MM), is synthesized and implemented on a field-programmable gate array (FPGA). MGS-QRD is restructured and augmented with parallelism directives prior to synthesizing the algorithm, which yielded an MGS-QRD hardware accelerator with high throughput. Modifications to the current TMI algorithm were also proposed, in which the removal of redundant computational tasks was done in order to speed up overall operation. Data dependencies in the MM algorithm were carefully considered such that appropriate parallelism directives were inserted, and matching the data flow of MM with MGS-QRD and TMI modules was also performed to accelerate the pseudoinverse computation. The results showed that the proposed pseudoinverse module is better than the naïve implementation which is composed of existing MGS-QRD, TMI and a standard MM in terms of maximum frequency (1.24Â speedup), hardware resources (48% of reduction of DSP usage), latency (23% reduction), and throughput (62% increase).

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Section: Previous Workmentioning

confidence: 99%

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

Tan

Ooi

Choo

et al. 2021

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…[1,2] As a result, code optimization techniques that accelerate loop execution are essential. [3,4] One technique for improving program execution time is loop unrolling. This technique involves replicating the loop body multiple times while adjusting the loop termination code.…”

Section: Introductionmentioning

confidence: 99%

Untitled

2023

Inf. Sci. Lett.

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Loop unrolling is a well-established code transformation technique that can improve the performance of a program at runtime. The key benefit of unrolling a loop is that it often requires fewer instruction executions than the original loop. However, determining the optimal number of loop unrolling is a critical concern. This paper presents a novel method for predicting the optimal unroll factor for a given program. Specifically, a dataset is constructed that includes the execution times of several programs with varying loop unroll factors. The programs are sourced from different benchmarks, such as Ploybench, Shooutout, and other programs. Similarity measures between the unseen program and the existing programs are computed, and the three most similar programs are identified. The unroll factor that led to the greatest reduction in execution time for the most similar programs is selected as the candidate for the unseen program. Experimental results demonstrate that the proposed method can enhance the performance of training programs for unroll factors of 2, 4, 6, and 8 by approximately 13%, 18%, 19%, and 21%, respectively. For the unseen programs, the speedup rate is approximately 37.7% for five programs.

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“…In Promrit and Suntiamorntut (2017), blob detection and HT were applied for road lane detection on the low-cost hardware device (Zynq-7000 family). To decrease the development time, Khongprasongsiri et al (2018) and Panda et al (2018) considered the optimization technique on HLS (loop-pipelining and loop-unrolling) to resolve the bottleneck computation and found out the suitable factor for loop algorithm. However, the HLS optimization techniques on hardware devices analysis with complex algorithms such as lane detection have not been completely analyzed yet.…”

Section: Introductionmentioning

confidence: 99%

Untitled

2021

JST

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In this work, we proposed High-Level Synthesis (HLS) optimization processes to improve the speed and the resource usage of complex algorithms, especially nested-loop. The proposed HLS optimization processes are divided into four steps: array sizing is performed to decrease the resource usage on Programmable Logic (PL) part, loop analysis is performed to determine which loop must be loop unrolling or loop pipelining, array partitioning is performed to resolve the bottleneck of loop unrolling and loop pipelining, and HLS interface is performed to select the best block level and port level interface for array argument of RTL design. A case study road lane detection was analyzed and applied with suitable optimization techniques to implement on the Xilinx Zynq-7000 family (Zybo ZC7010-1) which was a low-cost FPGA. From the experimental results, our proposed method reaches 6.66 times faster than the primitive method at clock frequency 100 MHz or about 6 FPS. Although the proposed methods cannot reach the standard real-time (25 FPS), they can instruct HLS developers for speed increasing and resource decreasing on an FPGA.

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Exploration of Loop Unroll Factors in High Level Synthesis

Cited by 7 publications

References 4 publications

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

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