Exploration of VLSI CAD researches for early design rule evaluation

Park, Hae‐Sim; Pan, Po-Cheng; Lucas, Robert J.

doi:10.1109/aspdac.2011.5722223

Cited by 2 publications

(1 citation statement)

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“…This corresponds to an absolute error of less than 1% on average. DRE area estimation has also been validated in [29] by comparison with actual layouts of a commercial 32nm standard-cell library.…”

Section: F Runtime and Validation Of Area Estimationmentioning

confidence: 99%

DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies

Ghaida

Gupta

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Design rules have been the primary contract between technology developers and designers and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. The framework essentially creates a virtual standard-cell library and performs the evaluation based on the virtual layouts. Due to the focus on the exploration of rules at an early stage of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). Such a framework can be used to co-evaluate and co-optimize design rules, patterning technologies, layout methodologies, and library architectures.

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Section: F Runtime and Validation Of Area Estimationmentioning

confidence: 99%