Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy efficiency. Unfortunately, low-voltage operation faces multiple challenges going forward. One such challenge is increased sensitivity to voltage fluctuations, which can trigger so-called "voltage emergencies" that can lead to errors. These fluctuations are caused by abrupt changes in power demand, triggered by processor activity variation as a function of workload. This paper examines the effects of voltage fluctuations on future many-core processors. With the increase in the number of cores in a chip, the effects of chip-wide activity fluctuation-such as that caused by global synchronization in multithreaded applications-overshadow the effects of core-level workload variability. Starting from this observation, we developed VRSync, a novel synchronization methodology that uses emergency-aware scheduling policies that reduce the slope of load fluctuations, eliminating emergencies. We show that VRSync is very effective at eliminating emergencies, allowing voltage guardbands to be significantly lowered, which reduces energy consumption by an average of 33%.

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Epoxy polymer concrete (EPC) has found increasing applications in infrastructure as a rising candidate among civil engineering materials. In most of its service environments, EPC is inevitably exposed to severe weather conditions, e.g., violent changes in temperature, rain, and ultraviolet (UV) radiation. In this paper, we designed an accelerated aging test for EPC, which includes periodic variation of temperature and water spray, as well as intensive UV-light irradiation, imitating the outdoor environment in South China. The experimental results show that the flexural performance of EPC is found deteriorate with the aging time. An aging process equivalent to four years (UV radiation dose) results in up to 8.4% reduction of flexural strength. To explore the mechanisms of observed performance degradation, the EPC specimen in the four-point-bending test is considered as a layered beam. The analysis indicates that the loss of flexural load-carrying capacity of an aged EPC beam is dominated by the reduction of mechanical properties of the surface layer. The mechanical properties of the surface layer are closely associated with the aging of epoxy mortar, which can be approximated as a reciprocal function of the aging time. By introducing damage to the surface layer into the layered beam, the proposed model demonstrates a good ability to predict the residual flexural strength of EPC during the aging process

This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.

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