Efficient analog layout prototyping by layout reuse with routing preservation

A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

“…Yet, it allows designers to decide the relevant solution from multiple candidates. Some of previous results were presented in [20]. Instead, this work appreciates the comparison with state-of-the-art.…”

“…In comparison with current migration mechanisms, Table I shows the different criterion to examine the disparity. There are 3 current migration styles, [5], [8] and [20], mentioned in Table I. For analog layout constraints, each approach is able to preserve specific constraints such as symmetry constraints and matching constraints.…”

“…For placement topology, [5] aims to keep the exactly same topology as the existing layout, [8] successfully produces multiple placement candidates and the placement in [20] is already given. For routing behavior, [5] only preserves the wires that belong to the symmetric devices or clusters which are symmetric on the original layout, [8] manually completes the routing section and [20] quickly produces routing prototype with routing preservation. Therefore, [5] generates single layout each time and [8] can generate multiple layout solutions.…”

“…Therefore, [5] generates single layout each time and [8] can generate multiple layout solutions. [20] produces multiple solutions from multiple placement results. To consider the Time-to-sign-off for overall flow, [5] and [8] are slower due to the routing generation and [20] facilitates the routing generation.…”

“…[20] produces multiple solutions from multiple placement results. To consider the Time-to-sign-off for overall flow, [5] and [8] are slower due to the routing generation and [20] facilitates the routing generation. In comparison, our approach consolidates the advantages from [8] for more opportunity and [20] for fast prototyping.…”