2015
DOI: 10.1109/tcad.2015.2418312
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A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation

Abstract: Analog layout generation in the advanced CMOS design is challenging by its increasing layout constraints and performance requirements. This situation becomes more intricate by the growing parasitic variability and manufacturing reliability. To facilitate the feasibility of template-based layout migration, this paper firstly introduces a layout preservation, which extracts placement and routing behaviors from an existing layout into a crossing graph via constrained Delaunay triangulation (CDT). And later this c… Show more

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Cited by 17 publications
(2 citation statements)
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“…They are a special kind of constraint for specifying the floorplan and sometimes the routing of analog blocks in a knowledge-based way. The underlying method of template description, its implementation, and solving strategy (e.g., by evolutionary approaches) is the subject of research [26][27][28][29][30]. As an example, the framework AIDA [13] utilizes templates and combines many academic works, from optimization algorithms to layout automation used for various designs.…”
Section: Templatesmentioning
confidence: 99%
“…They are a special kind of constraint for specifying the floorplan and sometimes the routing of analog blocks in a knowledge-based way. The underlying method of template description, its implementation, and solving strategy (e.g., by evolutionary approaches) is the subject of research [26][27][28][29][30]. As an example, the framework AIDA [13] utilizes templates and combines many academic works, from optimization algorithms to layout automation used for various designs.…”
Section: Templatesmentioning
confidence: 99%
“…Adapted from [53]. Chin and Pan et al (2013-15) [62][63] intended to fully preserve the routing behavior of the legacy design by using a constrained Delaunay triangulation (CDT) algorithm[64], which represents the correlation between routing and placement into a planar straight line graph. First, placement and routing paths are decomposed with a set of triangles, as illustrated in Fig.6(b) for a layout diagram with two blocks and one routing path in Fig.6(a).…”
mentioning
confidence: 99%