Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables the development of highly technology-independent analog circuit generators applicable in multiple design environments. IIP Generators are parameterizable descriptions of each view of an analog block, i.e., layout, schematic, and symbol. They allow the adaptation of complex layouts within seconds to minutes in order to incorporate hardly estimable parasitics and further considerations into the design flow. Due to the abstract generator description, valid design data is created for very different technologies such as 28 nm and 180 nm bulk CMOS, 28 nm FD-SOI, and others. The design experiment shows that procedural generators can be an effective tool for the efficient design of analog integrated circuits

Analog layout design is a costly and error-prone task since analog synthesis is still far from applicable. It is expected that procedural bottom-up generators managing constructive tasks will be part of future synthesis flows. Generators contain expert knowledge implicitly within complex and hard-to-understand source code. Due to a lack of explicit layout definition and uncaptured design intent, generator layouts can hardly be adapted by constructive algorithms directly. Thus, synthesis flows need to adapt layout blocks by varying generator parameters which results in computation-expensive optimization. This paper introduces MESH—a software structure to define detailed and flexible layout generators explicitly. Using MESH, just a few lines of code describe complex layouts while all relations and design intents, such as element positions and routing styles, are captured through abstract commands. As a result, generators are created fast with less programming errors, and constructive algorithms can modify the generator structure directly

Various analog design automation attempts have addressed the shortcomings of the still largely manual and, thus, inefficient and risky analog design approach. These methods can roughly be divided into synthesis and procedural generation. An important key aspect has, however, rarely been considered: usability. While synthesis requires sophisticated constraints, procedural generators require expert programmers. Both prevent users from adopting the respective method. Thus, we propose a new approach to automatically create procedural generators in a user-driven way. First, analog generators, which also create symbols and layouts, are utilized during schematic entry to encapsulate common analog building blocks. Second, automatic code creation builds a hierarchical generator for all views with the schematic as input. Third, the approach links the building block generators with the layout through an object-oriented template library that is accessible through generator parameters, allowing the user to control the arrangement. No programming is required to reach this state. We believe that our approach will significantly ease the transition of analog designers to procedural generation. At the same time, the templates allow for a “bridge” to open frameworks and synthesis approaches so that the methodologies can be both better spread and combined. This way, comprehensive frameworks of both synthesis-based and procedural-based analog automation methods can be built in a user-driven way, and designers are enabled to gain early layout insight and ease IP reusability.

This paper introduces a novel placement methodology for a common-centroid (CC) pattern generator. It can be applied to various integrated circuit (IC) elements, such as transistors, capacitors, diodes, and resistors. The proposed method consists of a constructive algorithm which generates an initial, close to the optimum, solution, and an iterative algorithm which is used subsequently, if the output of constructive algorithm does not satisfy the desired criteria. The outcome of this work is an automatic CC placement algorithm for IC element arrays. Additionally, the paper presents a method for the CC arrangement evaluation. It allows for evaluating the quality of an array, and a comparison of different placement methods

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