Fast analog layout prototyping for nanometer design migration

Abstract

This paper presents an analog layout migration methodology to quickly provide multiple layouts while keeping similar or better circuit performance. Unlike previous works that often generate a single layout that has exactly the same topology with the original layout, this new migration algorithm is able to provide results with different aspect ratios. First, various placement constraints, including topology, matching, and symmetry, are extracted from the original layout. The extracted constraints are hierarchically stored into a topology slicing tree. Placement is performed from the bottom tree nodes to the root tree node. In each tree node, multiple placements for the subtree are recorded. All possible placements under the constraints are recorded in the root node. This algorithm has been successfully applied to a variable gain amplifier and a folded cascode operational amplifier migrating from UMC 90nm to UMC 65nm. The experimental results validate that our approach can provide reasonable layouts, even a better result almost in no time.

Performance-driven analog placement considering monotonic current paths

“…Lai and Wong [26] further stated that the slicing trees can represent both slicing and non-slicing floorplans by integrating the compaction technique. Some other previous works [22,23] also showed that it is very efficient to apply the slicing-tree representation to design/layout migration and fixed-outline floorplanning. Therefore, it is desirable to explore analog placement using the slicing trees.…”

“…• We augment the slicing-tree representation [21], which has been shown to be very efficient in design/layout migration [22] and fixed-outline floorplanning [23], to model the symmetryisland placement. To our best knowledge, none of the previous works presented any symmetric-feasible condition in the slicing trees.…”

Laser

“…Previous works did not consider the required routing resource in the placement stage [8][9][10] or used an unfaithful congestion to adjust the generated placement [12][13][14]. To accurately predict the required routing resource during placement and generate nonstochastic placements, a routability-aware analog placement flow is proposed.…”

“…In the literature, layout automation techniques for analog circuits are also a popular research direction [8][9][10][11][12][13][14]. In recent years, many researches [8][9][10] focus on studying the analog placement problem to consider the extra layout constraints such as matching, proximity, etc. The succeeding routing issue is often not considered due to the small number of nets in analog circuits.…”

“…In order to reduce the parasitic capacitance and crosstalk effect, the routing nets above the active area of the devices are often avoided in the routing step [11]. Previous works [8][9][10] do not consider the routing resource in the placement stage and will incur compact placements which are not practical in analog designs. Previous works [12][13][14] perform congestion-driven adjustments during placement.…”