Laser

Abstract

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizinglayout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

Analog Integrated Circuit Routing Techniques: An Extensive Review

“…Another limitation pointed to both is that since designer knowledge is followed, no explicit parasitic impact due to the routing is accounted for during generation, which can lead to unforeseen design iterations. This aspect can be bypassed by its successful application within PiS/LaS flows [29]- [37], [78]- [82], but at the cost of execution time. SPfGs are closer to digital IC routing, and are immensely popular with two bursts of innovation in the 1990's and 2010's.…”

“…Likewise, in [81], LDS [55] was used for the LaS of a folded cascode OTA on a 0.13-μm technology node, where a commercial extractor also computed the interconnect parasitics. A final note is left on LASER (Layout-aware Analog Synthesis Environment on Laker, 2013-15) [82] [83], which provides a user-friendly graphical user interface (GUI) to assist the designer in iterative steps required on a LiS flow. On LASER, predefined templates for different circuit topologies can be easily converted into Synopsys' Laker [84] scripts.…”

A Placement and Routing Method for Layout Generation of CMOS Operational Amplifiers Using Multi-Objective Evolutionary Algorithm Based on Decomposition

“…Parametric generators are used that code the whole layout of the circuit to increase execution speed. However, their definition is time-consuming and the solutions for devices' sizes may differ from the ones intended in the definition step [21], [22], [23]. In Ref [24], a predefined floorplan template supported by a slicing tree is used.…”

Analog Circuits Sizing Using Multi-Objective Evolutionary Algorithm Based on Decomposition

“…Several analog layout-aware sizing methods have been introduced in the literature. A CAD tools supporting layout aware circuit sizing is introduced in [29]. But, some of the layout parasitics are not considered.…”