Exploring architectural heterogeneity in intelligent vision systems

Chandramoorthy, Nanchini; Tagliavini, Giuseppe; Irick, Kevin; Pullini, Antonio; Advani, Siddharth; Habsi, Sulaiman Al; Cotter, Matthew; Sampson, John J.; Narayanan, Vijaykrishnan; Benini, Luca

doi:10.1109/hpca.2015.7056017

Cited by 24 publications

(12 citation statements)

References 33 publications

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“…Yesil et al [21] surveyed existing custom accelerators and integration techniques for accelerator-rich systems in the context of data centers, but without a quantitative study as we did. Chandramoorthy et al [5] examined the performance of different design points including tightly coupled accelerators (TCAs) and loosely coupled accelerators (LCAs) customized for computer vision applications. Cotat et al [9] specifically analyzed the integration and interaction of TCAs and LCAs at different levels in the memory hierarchy.…”

Section: Related Workmentioning

confidence: 99%

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Choi

Cong

Fang

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

106

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CPU-FPGA heterogeneous acceleration platforms have shown great potential for continued performance and energy efficiency improvement for modern data centers, and have captured great attention from both academia and industry. However, it is nontrivial for users to choose the right platform among various PCIe and QPI based CPU-FPGA platforms from different vendors. This paper aims to find out what microarchitectural characteristics affect the performance, and how. We conduct our quantitative comparison and in-depth analysis on two representative platforms: QPI-based Intel-Altera HARP with coherent shared memory, and PCIe-based Alpha Data board with private device memory. We provide multiple insights for both application developers and platform designers.

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Section: Related Workmentioning

confidence: 99%

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

Choi

Cong

Fang

et al. 2016

Proceedings of the 53rd Annual Design Automation Conference

106

View full text Add to dashboard Cite

show abstract

“…The base architecture with several SIMD units or Processing Elements (PEs) with a varying degree of customization from general purpose to specialized kernels for common computer vision tasks in every SIMD unit (e.g. convolution, gradient or max-min suppression operators) is the approach followed today in many intelligent vision systems (see [6] and references therein). In this context, general purpose SIMD units could be configured as many core clusters for MIMD configuration.…”

Section: Related Workmentioning

confidence: 99%

PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

Nieto

Vilariño

Brea

2016

IEEE Trans. Comput.

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Computer vision applications have a large disparity in operations, data representation and memory access patterns from the early vision stages to the final classification and recognition stages. A hardware system for computer vision has to provide high flexibility without compromising performance, exploiting massively spatial-parallel operations but also keeping a high throughput on data-dependent and complex program flows. Furthermore, the architecture must be modular, scalable and easy to adapt to the needs of different applications. Keeping this in mind, a hybrid SIMD/MIMD architecture for embedded computer vision is proposed. It consists of a coprocessor designed to provide fast and flexible computation of demanding image processing tasks of vision applications. A 32-bit 128-unit device was prototyped on a Virtex-6 FPGA which delivers a peak performance of 19.6 GOP/s and 7.2 W of power dissipation.

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“…As the complexity of these applications and the resolution of images continue to increase, conventional homogeneous architectures (such as multi-core CPU/GPU) are constrained due to an excessive long latency and significant power dissipation [7,8,9]. To efficiently process these applications, heterogeneous architectures have been proposed with pre-processing and inference cores [7,8,9,10,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

A Technique for Approximate Communication in Network-on-Chips for Image Classification

Chen¹,

Liu²,

Lombardi³

et al. 2021

Preprint

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Approximation is an effective technique for reducing power consumption and latency of on-chip communication in many computing applications. However, existing approximation techniques either achieve modest improvements in these metrics or require retraining after approximation, such when convolutional neural networks (CNNs) are employed. Since classifying many images introduces intensive on-chip communication, reductions in both network latency and power consumption are highly desired. In this paper, we propose an approximate communication technique (ACT) to improve the efficiency of on-chip communications for image classification applications. The proposed technique exploits the error-tolerance of the image classification process to reduce power consumption and latency of on-chip communications, resulting in better overall performance for image classification computation. This is achieved by incorporating novel quality control and data approximation mechanisms that reduce the packet size. In particular, the proposed quality control mechanisms identify the error-resilient variables and automatically adjust the error thresholds of the variables based on the image classification accuracy. The proposed data approximation mechanisms significantly reduce packet size when the variables are transmitted. The proposed technique reduces the number of flits in each data packet as well as the on-chip communication, while maintaining an excellent image classification accuracy. The cycle-accurate simulation results show that ACT achieves 23% in network latency reduction and 24% in dynamic power reduction compared to the existing approximate communication technique with less than 0.99% classification accuracy loss.

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Exploring architectural heterogeneity in intelligent vision systems

Cited by 24 publications

References 33 publications

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms

PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

A Technique for Approximate Communication in Network-on-Chips for Image Classification

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